PROTEUS: A Tool to generate pipelined Number Theoretic Transform Architectures for FHE and ZKP applications. - Florian Hirner; Ahmet Can Mert; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2023)

A Hardware Implementation of MAYO Signature Scheme. - Florian Hirner; Michael Streibl; Ahmet Can Mert; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2023)

Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption. - Florian Krieger; Florian Hirner; Ahmet Can Mert; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2023)

Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms. - Florian Hirner; Michael Streibl; Florian Krieger; Ahmet Can Mert; Sujoy Sinha Roy (CCS, 2024)

Orion's Ascent: Accelerating Hash-Based Zero Knowledge Proof on Hardware Platforms. - Florian Hirner; Florian Krieger; Constantin Piber; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2024)

OpenNTT: An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE. - Florian Krieger; Florian Hirner; Ahmet Can Mert; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2024)

Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing. - Florian Krieger; Florian Hirner; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2024)

Proteus: A Pipelined NTT Architecture Generator. - Florian Hirner; Ahmet Can Mert; Sujoy Sinha Roy (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication. - Florian Hirner; Florian Krieger; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2025)