An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study. - Pasquale Davide Schiavone; Ernesto Sánchez 001; Annachiara Ruospo; Francesco Minervini; Florian Zaruba; Germain Haugou; Luca Benini (VLSI-SoC, 2018)

The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance. - Florian Zaruba; Fabian Schuiki; Stefan Mach; Luca Benini (ICECS, 2019)

A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI. - Stefan Mach; Fabian Schuiki; Florian Zaruba; Luca Benini (VLSI-SoC, 2019)

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology. - Florian Zaruba; Luca Benini (CoRR, 2019)

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. - Matheus A. Cavalcante; Fabian Schuiki; Florian Zaruba; Michael Schaffner; Luca Benini (CoRR, 2019)

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. - Florian Zaruba; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2019)

BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. - Jonathan Balkind; Katie Lim; Michael Schaffner; Fei Gao 016; Grigory Chirkov; Ang Li 011; Alexey Lavrov; Tri M. Nguyen 002; Yaosheng Fu; Florian Zaruba; Kunal Gulati; Luca Benini; et al. (ASPLOS, 2020)

ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. - Andreas Kurth; Samuel Riedel; Florian Zaruba; Torsten Hoefler; Luca Benini (DAC, 2020)

A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. - Florian Zaruba; Fabian Schuiki; Luca Benini (Hot Chips Symposium, 2020)

Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology. - Alfio Di Mauro; Florian Zaruba; Fabian Schuiki; Stefan Mach; Luca Benini (ISCAS, 2020)

Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. - Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini (CoRR, 2020)

FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. - Stefan Mach; Fabian Schuiki; Florian Zaruba; Luca Benini (CoRR, 2020)

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. - Florian Zaruba; Fabian Schuiki; Luca Benini (CoRR, 2020)

Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. - Matheus A. Cavalcante; Fabian Schuiki; Florian Zaruba; Michael Schaffner; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. - Paul Scheffler; Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini (DATE, 2021)

A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. - Thomas Benz; Luca Bertaccini; Florian Zaruba; Fabian Schuiki; Frank K. Gürkaynak; Luca Benini (ESSCIRC, 2021)

Banshee: A Fast LLVM-Based RISC-V Binary Translator. - Samuel Riedel; Fabian Schuiki; Paul Scheffler; Florian Zaruba; Luca Benini (ICCAD, 2021)

Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. - Luca Bertaccini; Matteo Perotti; Stefan Mach; Pasquale Davide Schiavone; Florian Zaruba; Luca Benini (ISCAS, 2021)

Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing. - Florian Zaruba; Fabian Schuiki; Luca Benini (IEEE Micro, 2021)

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. - Fabian Schuiki; Florian Zaruba; Torsten Hoefler; Luca Benini (IEEE Trans. Computers, 2021)

Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. - Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini (IEEE Trans. Computers, 2021)

FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. - Stefan Mach; Fabian Schuiki; Florian Zaruba; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Energy-efficient high-performance computing. - Florian Zaruba (Hartung-Gorre Verlag, 2021)

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. - Andreas Kurth; Wolfgang Rönninger; Thomas Benz; Matheus A. Cavalcante; Fabian Schuiki; Florian Zaruba; Luca Benini (IEEE Trans. Computers, 2022)

Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU. - Gianmarco Ottavi; Florian Zaruba; Luca Benini; Davide Rossi (DSD, 2023)

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. - Paul Scheffler; Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini (IEEE Trans. Parallel Distributed Syst., 2023)

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. - Pascal Alexander Hager; Bert Moons; Stefan Cosemans; Ioannis A. Papistas; Bram Rooseleer; Jeroen Van Loon; Roel Uytterhoeven; Florian Zaruba; Spyridoula Koumousi; Milos Stanisavljevic; Stefan Mach; Sebastiaan Mutsaards; et al. (ISSCC, 2024)