An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. - Foong-Charn Chang; Chin-Fu Chen; Prasad Subramaniam (DAC, 1988)

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. - Lun Ye; Foong-Charn Chang; Peter Feldmann; Rakesh Chadha; Nagaraj Ns; Frank Cano (DATE, 1999)