A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (ISSCC, 2010)

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (IEEE J. Solid State Circuits, 2010)