A set of programs for MOS design. - G. Sakauye; Anna Lubiw; J. Royle; R. Epplett; Jeffrey Tweedale; E. S. Y. Shew; E. Attfield; Franc Brglez; Philip S. Wilcox (DAC, 1981)

Digital Signal Processing Considerations in Filter-Codec Testing. - Franc Brglez (ITC, 1981)

Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. - Franc Brglez; Philip Pownall; Robert Hum (ITC, 1984)

A Fast Fault Grader: Analysis and Applications. - Franc Brglez (ITC, 1985)

Fault Coverage Tools: Case Studies. - Franc Brglez (ITC, 1985)

Accelerated Transition Fault Simulation. - Michael H. Schultz; Franc Brglez (DAC, 1987)

Testability-Driven Random Test-Pattern Generation. - Robert Lisanke; Franc Brglez; Aart J. de Geus; David Gregory (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

A modular scan-based testability system. - Franc Brglez; David Bryan; John D. Calhoun; Robert Lisanke (ICCD, 1988)

McMAP: a fast technology mapping procedure for multi-level logic synthesis. - Robert Lisanke; Franc Brglez; Gershon Kedem (ICCD, 1988)

Boundary Scan with Cellular-Based Built-In Self-Test. - Clay Gloster; Franc Brglez (ITC, 1988)

Hardware-Based Weighted Random Pattern Generation for Boundary Scan. - Franc Brglez; Gershon Kedem; Clay Gloster (ITC, 1989)

A Framework and Method for Hierarchical Test Generation. - John D. Calhoun; Franc Brglez (ITC, 1989)

Boundary scan with built-in self-test. - Clay S. Gloster Jr.; Franc Brglez (IEEE Des. Test, 1989)

Corolla Based Circuit Partitioning and Resynthesis. - Sujit Dey; Franc Brglez; Gershon Kedem (DAC, 1990)

Built-in self-test with weighted random pattern hardware. - Franc Brglez; Clay S. Gloster Jr.; Gershon Kedem (ICCD, 1990)

OASIS: a silicon compiler for semi-custom design. - Gershon Kedem; Franc Brglez; Krzysztof Kozminski (RSP, 1990)

Partitioning Sequential Circuits for Logic Optimization. - Sujit Dey; Franc Brglez; Gershon Kedem (ICCD, 1991)

Identification and Resynthesis of Pipelines in Sequential Networks. - Sujit Dey; Franc Brglez; Gershon Kedem (VLSI, 1991)

Circuit partitioning for logic synthesis. - Sujit Dey; Franc Brglez; Gershon Kedem (IEEE J. Solid State Circuits, 1991)

Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. - Ulf Schlichtmann; Franc Brglez; Michael Hermann (DAC, 1992)

Cellular scan test generation for sequential circuits. - Clay S. Gloster Jr.; Franc Brglez (EURO-DAC, 1992)

Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. - Matthew Melton; Franc Brglez (ITC, 1992)

Cost Minimization of Partitions into Multiple Devices. - Roman Kuznar; Franc Brglez; Krzysztof Kozminski (DAC, 1993)

A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema? - Franc Brglez (IEEE Des. Test Comput., 1993)

Transformations and resynthesis for testability of RT-level control-data path specifications. - Subhrajit Bhattacharya; Franc Brglez; Sujit Dey (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Clock Period Optimization During Resource Sharing and Assignment. - Subhrajit Bhattacharya; Sujit Dey; Franc Brglez (DAC, 1994)

Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. - Subhrajit Bhattacharya; Sujit Dey; Franc Brglez (DAC, 1994)

Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. - Roman Kuznar; Franc Brglez; Baldomir Zajc (DAC, 1994)

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. - Roman Kuznar; Baldomir Zajc; Franc Brglez (EURO-DAC, 1994)

Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. - Bernhard Rohfleisch; Franc Brglez (EDAC-ETC-EUROASIC, 1994)

A Functionality Fault Model: Feasibility and Applications. - Andrej Zemva; Franc Brglez; Krzysztof Kozminski; Baldomir Zajc (EDAC-ETC-EUROASIC, 1994)

Provably correct high-level timing analysis without path sensitization. - Subhrajit Bhattacharya; Sujit Dey; Franc Brglez (ICCAD, 1994)

Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities. - Phil Allen; Franc Brglez; Hal Carter; Robert Caverly; Jerry Dillion; Albert Lo; Ron Lomax; John Oldfield; Cesar Pina; T. J. Wilkinson (SIGARCH Comput. Archit. News, 1994)

Partial scan selection for user-specified fault coverage. - Clay Gloster; Franc Brglez (EURO-DAC, 1995)

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. - Roman Kuznar; Franc Brglez (ICCAD, 1995)

Detectable perturbations: a paradigm for technology-specific multi-fault test generation. - Andrej Zemva; Franc Brglez (VTS, 1995)

Fast true delay estimation during high level synthesis. - Subhrajit Bhattacharya; Sujit Dey; Franc Brglez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Executable Workflows: A Paradigm for Collaborative Design on the Internet. - Hemang Lavana; Amit Khetawat; Franc Brglez; Krzysztof Kozminski (DAC, 1997)

Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments. - Hemang Lavana; Amit Khetawat; Franc Brglez (GROUP, 1997)

Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. - Nevin Kapur; Debabrata Ghosh; Franc Brglez (ISPD, 1997)

Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. - Debabrata Ghosh; Nevin Kapur; Franc Brglez; Justin E. Harlow III (DATE, 1998)

Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. - Justin E. Harlow III; Franc Brglez (FMCAD, 1998)

Design of experiments in BDD variable ordering: lessons learned. - Justin E. Harlow III; Franc Brglez (ICCAD, 1998)

WebWise Tcl/Tk: A Safe-Tcl/Tk-based Toolkit Enhanced for the World Wide Web. - Hemang Lavana; Franc Brglez (Tcl/Tk Conference, 1998)

Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. - Subhrajit Bhattacharya; Sujit Dey; Franc Brglez (ACM Trans. Design Autom. Electr. Syst., 1998)

Heuristics and Experimental Design for Bigraph Crossing Number Minimization. - Matthias F. M. Stallmann; Franc Brglez; Debabrata Ghosh (ALENEX, 1999)

Design of experiments in CAD: context and new data sets for ISCAS'99. - Franc Brglez; Rolf Drechsler (ISCAS (6), 1999)

Equivalence classes of circuit mutants for experimental design. - Debabrata Ghosh; Franc Brglez (ISCAS (6), 1999)

Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. - Justin E. Harlow III; Franc Brglez (ISCAS (6), 1999)

User-configurable experimental design flows on the web: the ISCAS'99 experiments. - Hemang Lavana; Franc Brglez; Robert B. Reese (ISCAS (6), 1999)

Evaluating iterative improvement heuristics for bigraph crossing minimization. - Matthias F. M. Stallmann; Franc Brglez; Debabrata Ghosh (ISCAS (6), 1999)

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. - Hemang Lavana; Franc Brglez; Robert B. Reese; Gangadhar Konduri; Anantha P. Chandrakasan (ICCD, 2000)

The Scientific Method and Design and Test. - Franc Brglez (IEEE Des. Test Comput., 2000)

A Universal Client for Distributed Networked Design and Computing. - Franc Brglez; Hemang Lavana (DAC, 2001)

Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. - Matthias F. M. Stallmann; Franc Brglez; Debabrata Ghosh (ACM J. Exp. Algorithmics, 2001)

Design of experiments and evaluation of BDD ordering heuristics. - Justin E. Harlow III; Franc Brglez (Int. J. Softw. Tools Technol. Transf., 2001)

A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation. - Xiao Yu Li; Matthias F. M. Stallmann; Franc Brglez (SAT, 2003)

Effective bounding techniques for solving unate and binate covering problems. - Xiao Yu Li; Matthias F. M. Stallmann; Franc Brglez (DAC, 2005)

On SAT instance classes and a method for reliable performance experiments with SAT solvers. - Franc Brglez; Xiao Yu Li; Matthias F. M. Stallmann (Ann. Math. Artif. Intell., 2005)

Performance testing of combinatorial solvers with isomorph class instances. - Franc Brglez; Jason A. Osborne (Experimental Computer Science, 2007)

High-contrast algorithm behavior: observation, hypothesis, and experimental design. - Matthias F. M. Stallmann; Franc Brglez (Experimental Computer Science, 2007)

On Self-Avoiding Walks across n-Dimensional Dice and Combinatorial Optimization: An Introduction. - Franc Brglez (CoRR, 2013)

Low-Autocorrelation Binary Sequences: on the Performance of Memetic-Tabu and Self-Avoiding Walk Solvers. - Borko Boskovic; Franc Brglez; Janez Brest (CoRR, 2014)

On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks. - Franc Brglez; Borko Boskovic; Janez Brest (CEC, 2017)

Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve them. - Borko Boskovic; Franc Brglez; Janez Brest (Appl. Soft Comput., 2017)

On Uncensored Mean First-Passage-Time Performance Experiments with Multiwalk in Rp: a New Stochastic Optimization Algorithm. - Franc Brglez (CoRR, 2018)

Asymptotic Experiments with Data Structures: Bipartite Graph Matchings and Covers. - Eason Li; Franc Brglez (CoRR, 2022)