Metis: An Integrated Morphing Engine CPU to Protect Against Side Channel Attacks. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi (IEEE Access, 2021)

A Flexible ASIC-Oriented Design for a Full NTRU Accelerator. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Ruggero Susella (ASP-DAC, 2023)

An Efficient Unified Architecture for Polynomial Multiplications in Lattice-Based Cryptoschemes. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Ruggero Susella (ICISSP, 2023)

A Versatile and Unified HQC Hardware Accelerator. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Ruggero Susella (ACNS Workshops (2), 2024)

A High Efficiency Hardware Design for the Post-Quantum KEM HQC. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Ruggero Susella (HOST, 2024)

Performance and Efficiency Exploration of Hardware Polynomial Multipliers for Post-Quantum Lattice-Based Cryptosystems. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Ruggero Susella (SN Comput. Sci., 2024)

High-Performance FPGA Accelerator for the Post-quantum Signature Scheme CROSS. - Patrick Karl; Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Georg Sigl (IACR Cryptol. ePrint Arch., 2025)

An Efficient and Unified RTL Accelerator Design for HQC-128, HQC-192, and HQC-256. - Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi (IEEE Trans. Computers, 2025)