A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. - Andrea Pallotta; Francesco Centurelli; Francesco Loriga; Alessandro Trifiletti (Broadband European Networks and Multimedia Services, 1998)

A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. - Andrea Pallotta; Francesco Centurelli; Alessandro Trifiletti (ISLPED, 2000)

A tree-like amplifier architecture for large gain-bandwidth product. - Marco Balsi; Francesco Centurelli; Salvatore Pennisi; Alessandro Trifiletti (ICECS, 2002)

Bipolar differential cell with improved bandwidth performance. - Marco Balsi; Francesco Centurelli; Salvatore Pennisi; Alessandro Trifiletti (ICECS, 2002)

Current output stage with improved CMRR. - Francesco Centurelli; Salvatore Pennisi; Alessandro Trifiletti (ICECS, 2003)

An accurate behavioral model of phase detectors for clock recovery circuits. - Marco Balsi; Francesco Centurelli; Giuseppe Scotti; Pasquale Tommasino; Alessandro Trifiletti (ISCAS (4), 2003)

Robust three-state PFD architecture with enhanced frequency acquisition capabilities. - Francesco Centurelli; Stefano Costi; Mauro Olivieri; Salvatore Pennisi; Alessandro Trifiletti (ISCAS (4), 2004)

A high-speed low-voltage phase detector for clock recovery from NRZ data. - Francesco Centurelli; Massimo Pozzoni; Giuseppe Scotti; Alessandro Trifiletti (ISCAS (4), 2004)

High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. - Francesco Centurelli; G. Lulli; Piero Marietti; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti (ISCAS (1), 2005)

Analytic transient solution of SCFL logic gates. - Alberto Maria Bersani; Francesco Centurelli; Luca Fontana; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2005)

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. - Francesco Centurelli; Alessandro Golfarelli; Jesus Guinea; Leonardo Masini; Damiana Morigi; Massimo Pozzoni; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis. - Marco Balsi; Francesco Centurelli; Piero Marietti; Giuseppe Scotti; Pasquale Tommasino; Alessandro Trifiletti; Giancarlo Valente (ISCAS, 2006)

A model for the distortion due to switch on-resistance in sample-and-hold circuits. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ISCAS, 2006)

Power-constrained Bandwidth Optimization in Cascaded Open-loop Amplifiers. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ECCTD, 2007)

A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications. - Francesco Centurelli; Andrea Simonetti; Alessandro Trifiletti (ECCTD, 2007)

CMOS Miller OTA with Body-Biased Output Stage. - Alfio Dario Grasso; Salvatore Pennisi; Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti (ECCTD, 2007)

A distortion model for pipeline Analog-to-Digital converters. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ISCAS, 2007)

A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. - Francesco Centurelli; Luca Giancane; Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti (PATMOS, 2007)

CMOS High-CMRR Current Output Stages. - Francesco Centurelli; Alfio Dario Grasso; Salvatore Pennisi; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data. - Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A gain-enhancing technique for very low-voltage amplifiers. - Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti (ISCAS, 2008)

A Simple Technique for Fast Digital Background Calibration of A/D Converters. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (EURASIP J. Adv. Signal Process., 2008)

Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies. - Francesco Centurelli; Pietro Monsurrò; Salvatore Pennisi; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A very low-voltage differential amplifier for opamp design. - Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti (ECCTD, 2011)

An MDAC architecture with low sensitivity to finite opamp gain. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ECCTD, 2011)

A class-AB flipped voltage follower output stage. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ECCTD, 2011)

A class-AB very low voltage amplifier and sample & hold circuit. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ECCTD, 2011)

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer. - Francesco Centurelli; Giuseppe Scotti; Pasquale Tommasino; Alessandro Trifiletti; Milena Djukanovic (MIXDES, 2014)

A wideband amplifier topology based on positive capacitive feedback. - Francesco Centurelli; Roberto Antonio Gualano; Alessandro Trifiletti (Microelectron. J., 2014)

Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks. - Simone Bongiovanni; Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti (J. Cryptogr. Eng., 2015)

A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier. - Francesco Centurelli; Pietro Monsurrò; Danilo Ruscio; Alessandro Trifiletti (MIXDES, 2016)

Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2016)

Power-efficient dynamic-biased CCII. - Gianluca Barile; L. Liberati; Giuseppe Ferri; Leonardo Pantoli; Vincenzo Stornelli; Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ECCTD, 2017)

A fully-differential class-AB OTA with CMRR improved by local feedback. - Francesco Centurelli; Pietro Monsurrò; Gaetano Parisi; Pasquale Tommasino; Alessandro Trifiletti (ECCTD, 2017)

Class-AB current conveyors based on the FVF. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti; Gianluca Barile; Giuseppe Ferri; Leonardo Pantoli; Vincenzo Stornelli (ECCTD, 2017)

On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks. - Francesco Centurelli; Pietro Monsurrò; Pasquale Tommasino; Alessandro Trifiletti (ECCTD, 2017)

Fully Differential Class-AB OTA with Improved CMRR. - Francesco Centurelli; Pietro Monsurrò; Gaetano Parisi; Pasquale Tommasino; Alessandro Trifiletti (J. Circuits Syst. Comput., 2017)

A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR. - Francesco Centurelli; Pietro Monsurrò; Gaetano Parisi; Pasquale Tommasino; Alessandro Trifiletti (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A low-power class-AB Gm-C biquad stage in CMOS 40nm technology. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ICECS, 2019)

High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2019)

0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias. - Danilo Cellucci; Francesco Centurelli; Valerio Di Stefano; Pietro Monsurrò; Salvatore Pennisi; Giuseppe Scotti; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2020)

Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors. - Francesco Centurelli; Pietro Monsurrò; Vincenzo Stornelli; Gianluca Barile; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2020)

An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response. - Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Pasquale Tommasino; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2020)

Delay models and design guidelines for MCML gates with resistor or PMOS load. - Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti; Gaetano Palumbo (Microelectron. J., 2020)

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. - Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti; Gaetano Palumbo (ISCAS, 2021)

A Detailed Model of the Switched-Resistor Technique. - Francesco Centurelli; Alessandro Fava; Giuseppe Scotti; Alessandro Trifiletti (IEEE Open J. Circuits Syst., 2021)

Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. - Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti; Gaetano Palumbo (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications. - Giandomenico Amendola; Luigi Boccia; Francesco Centurelli; Pascal Chevalier 002; Alessandro Fonte; Carmine Mustacchio; Andrea Pallotta; Pasquale Tommasino; Antonio Traversa; Alessandro Trifiletti (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. - Francesco Centurelli; Giuseppe Scotti; Gaetano Palumbo (IEEE Trans. Very Large Scale Integr. Syst., 2021)

High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain. - Riccardo Della Sala; Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti (PRIME, 2022)

Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications. - Riccardo Della Sala; Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti (PRIME, 2022)

A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs. - Francesco Centurelli; Gianluca Giustolisi; Salvatore Pennisi; Giuseppe Scotti (IEEE Access, 2022)

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs. - Riccardo Della Sala; Francesco Centurelli; Giuseppe Scotti (IEEE Access, 2022)

A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers. - Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Pasquale Tommasino; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design. - Riccardo Della Sala; Francesco Centurelli; Giuseppe Scotti (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

General Approach to the Calibration of Innovative MFP Multichannel Digitizers. - Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti; Mauro D'Arco; Leopoldo Angrisani (IEEE Trans. Instrum. Meas., 2022)

CMOS Adaptive Biased Second Generation Voltage Conveyor. - Gianluca Barile; Vincenzo Stornelli; Leonardo Pantoli; Davide Colaiuda; Francesco Centurelli; Pasquale Tommasino; Alessandro Trifiletti; Giuseppe Ferri (BATS, 2023)

A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing. - Cristian Bocciarelli; Francesco Centurelli; Riccardo Della Sala; Valerio Spinogatti; Alessandro Trifiletti (PRIME, 2023)

A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates. - Riccardo Della Sala; Cristian Bocciarelli; Francesco Centurelli; Valerio Spinogatti; Alessandro Trifiletti (PRIME, 2023)

Robust Body Biasing Techniques for Dynamic Comparators. - Valerio Spinogatti; Cristian Bocciarelli; Francesco Centurelli; Riccardo Della Sala; Alessandro Trifiletti (PRIME, 2023)

Wide-Band Shared LNA for Large Scale Neural Recording Applications. - Alessandro Fava; Francesco Centurelli; Andrea Vittimberga; Giuseppe Scotti (SMACD, 2023)

A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s. - Francesco Centurelli; Pietro Monsurrò; Pasquale Tommasino; Alessandro Trifiletti (IEEE Access, 2023)

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations. - Riccardo Della Sala; Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti (IEEE Access, 2023)

An Improved Strong Arm Comparator With Integrated Static Preamplifier. - Valerio Spinogatti; Riccardo Della Sala; Cristian Bocciarelli; Francesco Centurelli; Alessandro Trifiletti (IEEE Access, 2023)

A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits. - Alessandro Fava; Francesco Centurelli; Giuseppe Scotti (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages. - Riccardo Della Sala; Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2023)

High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration. - Cristian Bocciarelli; Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti; Valerio Spinogatti; Pasquale Tommasino; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 17 GHz inductorless low-pass filter based on a quasi-Sallen-Key approach. - Cristian Bocciarelli; Francesco Centurelli; Pietro Monsurrò; Valerio Spinogatti; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2023)

Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage. - Riccardo Della Sala; Cristian Bocciarelli; Valerio Spinogatti; Francesco Centurelli; Alessandro Trifiletti (PRIME, 2024)

A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs. - Riccardo Della Sala; Francesco Centurelli; Giuseppe Scotti (PRIME, 2024)

A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme. - Valerio Spinogatti; Cristian Bocciarelli; Lorenzo Eusebio; Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti (PRIME, 2024)

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation. - Riccardo Della Sala; Francesco Centurelli; Pietro Monsurrò; Giuseppe Scotti (IEEE Access, 2024)

A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier. - Riccardo Della Sala; Francesco Centurelli; Giuseppe Scotti (IEEE Access, 2024)

Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. - Riccardo Della Sala; Francesco Centurelli; Giuseppe Scotti; Gaetano Palumbo (IEEE Access, 2024)

A Novel Ultra-Low-Power, Tunable, LPF and BPF Biquad Based on New Fully Differential Folded-Gain-Boosting. - Matteo Lombardo; Francesco Centurelli; Pietro Monsurrò; Alessandro Trifiletti (ISCAS, 2025)

0.5 V Digitally-Tunable Filters for Biomedical Applications Exploiting Segmented Duty-Cycled Resistors. - Alessandro Fava; Francesco Centurelli; Giuseppe Scotti (IEEE Access, 2025)

Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF. - Riccardo Della Sala; Davide Bellizia; Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)