Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. - Francesco Lorenzelli; Zhan Gao; Joe Swenton; Santosh Malagi; Erik Jan Marinissen (ETS, 2021)

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. - Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Slimane Boutobza; Cheng-Wen Wu; Georges G. E. Gielen; Erik Jan Marinissen (3DIC, 2023)

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. - Francesco Lorenzelli; Asser Elsayed; Clement Godfrin; Alexander Grill; Stefan Kubicek; Ruoyu Li; Michele Stucchi; Danny Wan; Kristiaan De Greve; Erik Jan Marinissen; Georges G. E. Gielen (ETS, 2023)

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. - Po-Yao Chuang; Francesco Lorenzelli; Erik Jan Marinissen (ITC-Asia, 2023)

Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. - Francesco Lorenzelli; Asser Elsayed; Clement Godfrin; Alexander Grill; Stefan Kubicek; Ruoyu Li; Michele Stucchi; Danny Wan; Kristiaan De Greve; Erik Jan Marinissen; Georges G. E. Gielen (ITC, 2023)

Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. - Po-Yao Chuang; Francesco Lorenzelli; Sreejit Chakravarty; Cheng-Wen Wu; Georges G. E. Gielen; Erik Jan Marinissen (VTS, 2023)

Test and Repair Improvements for UCIe. - Tsung-Hsuan Wang; Po-Yao Chuang; Francesco Lorenzelli; Erik Jan Marinissen (ETS, 2024)

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency. - Po-Yao Chuang; Francesco Lorenzelli; Cheng-Wen Wu; Erik Jan Marinissen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)