Random Telegraph Signal noise properties of HfOx RRAM in high resistive state. - Francesco Maria Puglisi; Paolo Pavan; Andrea Padovani; Luca Larcher; Gennadi Bersuker (ESSDERC, 2012)

Random telegraph noise analysis to investigate the properties of active traps of HfO2-based RRAM in HRS. - Francesco Maria Puglisi; Paolo Pavan; Andrea Padovani; Luca Larcher (ESSDERC, 2013)

A compact model of hafnium-oxide-based resistive random access memory. - Francesco Maria Puglisi; Paolo Pavan; Andrea Padovani; Luca Larcher (ICICDT, 2013)

Analysis of RTN and cycling variability in HfO2 RRAM devices in LRS. - Francesco Maria Puglisi; Paolo Pavan; Luca Larcher; Andrea Padovani (ESSDERC, 2014)

Characterization of anomalous Random Telegraph Noise in Resistive Random Access Memory. - Francesco Maria Puglisi; Luca Larcher; Andrea Padovani; Paolo Pavan (ESSDERC, 2015)

A microscopic physical description of RTN current fluctuations in HfOx RRAM. - Francesco Maria Puglisi; Paolo Pavan; Luca Vandelli; Andrea Padovani; Matteo Bertocchi; Luca Larcher (IRPS, 2015)

Probing defects generation during stress in high-κ/metal gate FinFETs by random telegraph noise characterization. - Francesco Maria Puglisi; Felipe Costantini; Ben Kaczer; Luca Larcher; Paolo Pavan (ESSDERC, 2016)

Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials. - Luca Larcher; Francesco Maria Puglisi; Andrea Padovani; Luca Vandelli; Paolo Pavan (PATMOS, 2016)

Bipolar Resistive RAM Based on HfO2: Physics, Compact Modeling, and Variability Control. - Francesco Maria Puglisi; Luca Larcher; Andrea Padovani; Paolo Pavan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Guidelines for a Reliable Analysis of Random Telegraph Noise in Electronic Devices. - Francesco Maria Puglisi; Paolo Pavan (IEEE Trans. Instrum. Meas., 2016)

A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design. - Francesco Maria Puglisi; Nicolo Zagni; Luca Larcher; Paolo Pavan (ESSDERC, 2017)

Measuring and analyzing Random Telegraph Noise in Nanoscale Devices: The case of resistive random access memories. - Francesco Maria Puglisi (NVMTS, 2017)

Variability and sensitivity to process parameters variations in InGaAs dual-gate ultra-thin body MOSFETs: A scaling perspective. - Nicolo Zagni; Francesco Maria Puglisi; Giovanni Verzellesi; Paolo Pavan (PATMOS, 2017)

Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact Model. - Francesco Maria Puglisi; Lorenzo Pacchioni; Nicolo Zagni; Paolo Pavan (ESSDERC, 2018)

SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model. - Francesco Maria Puglisi; Tommaso Zanotti; Paolo Pavan (ESSDERC, 2019)

Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations. - Tommaso Zanotti; Francesco Maria Puglisi; Paolo Pavan (AICAS, 2020)

Trap Dynamics Model Explaining the RON Stress/Recovery Behavior in Carbon-Doped Power AlGaN/GaN MOS-HEMTs. - Nicolò Zagni; Alessandro Chini; Francesco Maria Puglisi; Paolo Pavan; Matteo Meneghini; Gaudenzio Meneghesso; Enrico Zanoni; Giovanni Verzellesi (IRPS, 2020)

Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise. - Tommaso Zanotti; Francesco Maria Puglisi; Paolo Pavan (IRPS, 2020)

Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices. - Tommaso Zanotti; Francesco Maria Puglisi; Paolo Pavan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories. - Tommaso Zanotti; Francesco Maria Puglisi; Paolo Pavan (IRPS, 2021)

Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories. - Francesco Maria Puglisi; Tommaso Zanotti; Paolo Pavan (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Defects Motion as the Key Source of Random Telegraph Noise Instability in Hafnium Oxide. - Sara Vecchi; Paolo Pavan; Francesco Maria Puglisi (ESSDERC, 2022)

Self-consistent Automated Parameter Extraction of RRAM Physics-Based Compact Model. - Tommaso Zanotti; Paolo Pavan; Francesco Maria Puglisi (ESSDERC, 2022)

Combining Experiments and a Novel Small Signal Model to Investigate the Degradation Mechanisms in Ferroelectric Tunnel Junctions. - Lorenzo Benatti; Paolo Pavan; Francesco Maria Puglisi (IRPS, 2022)

The Relevance of Trapped Charge for Leakage and Random Telegraph Noise Phenomena. - Sara Vecchi; Paolo Pavan; Francesco Maria Puglisi (IRPS, 2022)

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. - Raffaele De Rose; Tommaso Zanotti; Francesco Maria Puglisi; Felice Crupi; Paolo Pavan; Marco Lanuzza (CoRR, 2022)

Effect of cycling on ultra-thin HfZrO4, ferroelectric synaptic weights. - Laura Bégon-Lours; Mattia Halter; Marilyne Sousa; Youri Popoff; Diana Dávila Pineda; Donato Francesco Falcone; Zhenming Yu; Steffen Reidt; Lorenzo Benatti; Francesco Maria Puglisi; Bert Jan Offrein (Neuromorph. Comput. Eng., 2022)

The Role of Defects and Interface Degradation on Ferroelectric HZO Capacitors Aging. - Lorenzo Benatti; Sara Vecchi; Milan Pesic; Francesco Maria Puglisi (IRPS, 2023)

A Unified Framework to Explain Random Telegraph Noise Complexity in MOSFETs and RRAMs. - Sara Vecchi; Paolo Pavan; Francesco Maria Puglisi (IRPS, 2023)

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges. - Nicolò Zagni; Francesco Maria Puglisi; Paolo Pavan; Muhammad Ashraful Alam (Proc. IEEE, 2023)

A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules. - Davide Florini; Daniela Gandolfi; Jonathan Mapelli; Lorenzo Benatti; Paolo Pavan; Francesco Maria Puglisi (IEEE Trans. Neural Networks Learn. Syst., 2024)

Design of a Temperature-Aware Voltage Generator for 2-Bit Read Operation in STT-MRAM Based SIMPLY Architecture. - Massimo Vatalaro; Vincenzo Maccaronio; Tommaso Zanotti; Erika Borellini; Felice Crupi; Francesco Maria Puglisi; Raffaele De Rose (ICICDT, 2025)

Design for Reliability of Multi-Bit Operations in RRAM-Based SIMPLY Logic-in-Memory Circuits. - Tommaso Zanotti; Erika Borellini; Massimo Vatalaro; Vincenzo Maccaronio; Paolo Pavan; Raffaele De Rose; Francesco Maria Puglisi (ICICDT, 2025)