A post-compiler approach to scratchpad mapping of code. - Federico Angiolini; Francesco Menichelli; Alberto Ferrero; Luca Benini; Mauro Olivieri (CASES, 2004)

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. - Francesco Menichelli; Mauro Olivieri; Luca Benini; Monica Donno; Labros Bisdounis (DATE, 2004)

A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems. - Luca Benini; Francesco Menichelli; Mauro Olivieri (IEEE Trans. Computers, 2004)

Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation. - Francesco Menichelli; Mauro Olivieri; Simone Smorfa; Irene Zaccardini (Circuits, Signals, and Systems, 2005)

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. - Luca Benini; Davide Bertozzi; Alessandro Bogliolo; Francesco Menichelli; Mauro Olivieri (J. VLSI Signal Process., 2005)

Tecniche di analisi e progetto di architetture di sistemi a microprocessore integrati su singolo chip caratterizzati da criticitaÌ€ nei consumi di potenza. - Francesco Menichelli (2005)

Side channel analysis resistant design flow. - Manfred Josef Aigner; Stefan Mangard; Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Thomas Popp; Giuseppe Scotti; Alessandro Trifiletti (ISCAS, 2006)

Testing power-analysis attack susceptibility in register-transfer level designs. - Marco Bucci; Raimondo Luzzi; Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Alessandro Trifiletti (IET Inf. Secur., 2007)

High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips. - Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Alessandro Trifiletti (IEEE Trans. Dependable Secur. Comput., 2008)

Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips. - Francesco Menichelli; Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2009)

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction. - Francesco Menichelli; Mauro Olivieri (Wirel. Sens. Netw., 2010)

Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. - Francesco Menichelli; Mauro Olivieri; Simone Smorfa (ISCAS, 2011)

Scalable virtual prototyping of distributed embedded control in a modern elevator system. - Alberto Ferrari; Marco Carloni; Alessandro Mignogna; Francesco Menichelli; David Ginsberg; Eelco Scholte; Dang Nguyen 005 (SIES, 2012)

Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (J. Comput. Networks Commun., 2012)

Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (ApplePies, 2013)

A Model-Based Methodology to Generate Code for Timer Units. - Marco Marazza; Francesco Menichelli; Mauro Olivieri; Orlando Ferrante; Alberto Ferrari (ApplePies, 2014)

A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems. - Francesco Menichelli; Mauro Olivieri (ApplePies, 2014)

A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (J. Comput. Networks Commun., 2014)

Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (ApplePies, 2015)

An Emulator for Approximate Memory Platforms Based on QEmu. - Francesco Menichelli; Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri (ApplePies, 2016)

The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. - Abdallah Cheikh; Gianmarco Cerutti; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2017)

Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. - Mauro Olivieri; Abdallah Cheikh; Gianmarco Cerutti; Antonio Mastrandrea; Francesco Menichelli (NGCAS, 2017)

Approximate Memory Support for Linux Early Allocators in ARM Architectures. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2018)

Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. - Giulia Stazi; Federica Silvestri; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2018)

Characterizing noise pulse effects on the power consumption of idle digital cells. - Mauro Olivieri; Usman Khalid; Antonio Mastrandrea; Francesco Menichelli (ISCAS, 2018)

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (NGCAS, 2018)

Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. - Giulia Stazi; Lorenzo Adani; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ISC Workshops, 2018)

A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. - Luigi Blasi; Francesco Vigli; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Quality Aware Selective ECC for Approximate DRAM. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2019)

Quality Aware Approximate Memory in RISC-V Linux Kernel. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (PRIME, 2019)

Full System Emulation of Approximate Memory Platforms with AppropinQuo. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (J. Low Power Electron., 2019)

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. - Marcello Barbirotta; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Luigi Blasi; Abdallah Cheikh; Stefano Sordillo; Fabio Di Gennaro; Mauro Olivieri (DFT, 2020)

Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Giuseppe Scotti; Mauro Olivieri (CoRR, 2020)

A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Mauro Olivieri (DFT, 2021)

Efficient Machine Learning Algorithm for Embedded Tactile Data Processing. - Moustafa Saleh; Ali Ibrahim; Francesco Menichelli; Yasser Mohanna; Maurizio Valle (ISCAS, 2021)

Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Giuseppe Scotti; Mauro Olivieri (IEEE Micro, 2021)

Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Saeid Jamili; Mauro Olivieri (ApplePies, 2022)

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. - Saeid Jamili; Abdallah Cheikh; Antonio Mastrandrea; Marcello Barbirotta; Francesco Menichelli; Marco Angioli; Mauro Olivieri (ApplePies, 2022)

Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (PRIME, 2022)

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (IEEE Access, 2022)

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Abdallah Cheikh; Saeid Jamili; Francesco Menichelli; Mauro Olivieri (ApplePies, 2023)

Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. - Marcello Barbirotta; Francesco Menichelli; Antonio Mastrandrea; Abdallah Cheikh; Marco Angioli; Saeid Jamili; Mauro Olivieri (ApplePies, 2023)

A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. - Saeid Jamili; Antonio Mastrandrea; Abdallah Cheikh; Marcello Barbirotta; Francesco Menichelli; Marco Angioli; Mauro Olivieri (ApplePies, 2023)

Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Abdallah Cheikh; Francesco Menichelli; Mauro Olivieri (ApplePies, 2024)

Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Francesco Menichelli; Abdallah Cheikh; Mauro Olivieri (DFT, 2024)

Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Francesco Menichelli; Abdallah Cheikh; Mauro Olivieri (DFT, 2024)

AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. - Marco Angioli; Saeid Jamili; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Antonello Rosato; Mauro Olivieri (IJCNN, 2024)

Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. - Marcello Barbirotta; Francesco Menichelli; Abdallah Cheikh; Antonio Mastrandrea; Marco Angioli; Mauro Olivieri (IEEE Access, 2024)

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. - Francesco Vigli; Marcello Barbirotta; Abdallah Cheikh; Francesco Menichelli; Antonio Mastrandrea; Mauro Olivieri (IEEE Access, 2024)

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Saeid Jamili; Mauro Olivieri (IEEE Trans. Computers, 2024)

HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems. - Marco Angioli; Antonello Rosato; Marcello Barbirotta; Rocco Martino; Francesco Menichelli; Mauro Olivieri (CoRR, 2025)

Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ACM Trans. Embed. Comput. Syst., 2025)