Low Power Strategy for a TFT Controller. - Giuseppe Notarangelo; Marco Gibilaro; Francesco Pappalardo 002; Agatino Pennisi; Gaetano Palumbo (DSD, 2002)

Evaluation on power reduction applying gated clock approaches. - Gaetano Palumbo; Francesco Pappalardo 002; S. Sannella (ISCAS (4), 2002)

An application-oriented analysis of power/precision trade-off in fixed and floating-point arithmetic units for VLSI processors. - Francesco Pappalardo 002; Giuseppe Visalli; Mirko Scarana (Circuits, Signals, and Systems, 2004)

Bus-switch coding for reducing power dissipation in off-chip buses. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (IEEE Trans. Very Large Scale Integr. Syst., 2004)

statistical analysis, for reducing the energy dissipation in a bus-switch encoder. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (Circuits, Signals, and Systems, 2005)

Design issues for bus switch systems in deep sub-micro metric CMOS technologies. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (Circuits, Signals, and Systems, 2005)

Encoding circuits for low power optical on-chip communications. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (ISCAS (5), 2005)

A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing. - Giuseppe Notarangelo; Francesco Pappalardo 002; Elena Salurso; Elio Guidetti (J. Low Power Electron., 2007)

Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units. - Mauro Olivieri; Francesco Pappalardo 002; Simone Smorfa; Giuseppe Visalli (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip. - Nathan Ickes; Yildiz Sinangil; Francesco Pappalardo 002; Elio Guidetti; Anantha P. Chandrakasan (ESSCIRC, 2011)

Fractional-order simulation tool for the brainstem vestibulo-ocular reflex (VOR). - Riccardo Caponetto; Giovanni Dongola; Francesco Pappalardo 002 (Signal Image Video Process., 2012)

Auto-Tuning and Fractional Order Controller Implementation on Hardware in the Loop System. - Riccardo Caponetto; Giovanni Dongola; Francesco Pappalardo 002; V. Tomasello (J. Optim. Theory Appl., 2013)

Using High-Level Synthesis to model System Verilog procedural timing controls. - Luca Ezio Pozzoni; Fabrizio Ferrandi; Loris Mendola; Alfio Antonino Palazzo; Francesco Pappalardo 002 (DATE, 2023)