Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs. - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (ACM Trans. Embed. Comput. Syst., 2019)

AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC. - Francesco Restuccia 002; Alessandro Biondi 001; Mauro Marinoni; Giorgiomaria Cicero; Giorgio C. Buttazzo (DAC, 2020)

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs. - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (ECRTS, 2020)

Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC. - Francesco Restuccia 002; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (FCCM, 2020)

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (Dagstuhl Artifacts Ser., 2020)

Isadora: Automated Information Flow Property Generation for Hardware Designs. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Ryan Kastner; Cynthia Sturton (ASHES@CCS, 2021)

Aker: A Design and Verification Framework for Safe and Secure SoC Access Control. - Francesco Restuccia 002; Andres Meza 001; Ryan Kastner (ICCAD, 2021)

Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms. - Francesco Restuccia 002; Alessandro Biondi 001 (RTSS, 2021)

A Methodology For Creating Information Flow Specifications of Hardware Designs. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Ryan Kastner; Cynthia Sturton (CoRR, 2021)

AKER: A Design and Verification Framework for Safe andSecure SoC Access Control. - Francesco Restuccia 002; Andres Meza 001; Ryan Kastner (CoRR, 2021)

Automating hardware security property generation: invited. - Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Sayak Ray; Jason M. Fung; Cynthia Sturton (DAC, 2022)

Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC. - Gerlando Sciangula; Francesco Restuccia 002; Alessandro Biondi 001; Giorgio C. Buttazzo (DSD, 2022)

PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms. - Gabriele Serra; Pietro Fara; Giorgiomaria Cicero; Francesco Restuccia 002; Alessandro Biondi 001 (RTAS, 2022)

A Remote Control System for Emergency Ventilators During SARS-CoV-2. - Michael Barrow; Francesco Restuccia 002; Mustafa S. Gobulukoglu; Enrico Rossi; Ryan Kastner (IEEE Embed. Syst. Lett., 2022)

Toward Hardware Security Property Generation at Scale. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Matthew Gregoire; Ryan Kastner; Cynthia Sturton (IEEE Secur. Priv., 2022)

ARTe: Providing real-time multitasking to Arduino. - Francesco Restuccia 002; Marco Pagani; Agostino Mascitti; Michael Barrow; Mauro Marinoni; Alessandro Biondi 001; Giorgio C. Buttazzo; Ryan Kastner (J. Syst. Softw., 2022)

Cut and Forward: Safe and Secure Communication for FPGA System on Chips. - Francesco Restuccia 002; Ryan Kastner (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. - Sohrab Aftabjahani; Mark Tehranipoor; Farimah Farahmandi; Bulbul Ahmed; Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Kaki Ryan; Nicole Fern; Jasper Van Woudenberg; Rajesh Velegalati; Cees-Bart Breunesse; et al. (VTS, 2023)

Security Verification of the OpenTitan Hardware Root of Trust. - Andres Meza 001; Francesco Restuccia 002; Jason Oberg; Dominic Rizzo; Ryan Kastner (IEEE Secur. Priv., 2023)

Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs. - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (IEEE Trans. Computers, 2023)

A Framework for Design, Verification, and Management of SoC Access Control Systems. - Francesco Restuccia 002; Andres Meza 001; Ryan Kastner; Jason Oberg (IEEE Trans. Computers, 2023)

Isadora: automated information-flow property generation for hardware security verification. - Calvin Deutschbein; Andres Meza 001; Francesco Restuccia 002; Ryan Kastner; Cynthia Sturton (J. Cryptogr. Eng., 2023)

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. - Thomas Benz; Alessandro Ottaviano; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Luca Benini (DATE, 2024)

eXpect: On the Security Implications of Violations in AXI Implementations. - Melisande Zonta-Roudes; Andres Meza 001; Nora Hinderling; Lucas Deutschmann; Francesco Restuccia 002; Ryan Kastner; Shweta Shinde (ICCAD, 2024)

CGRA4ML: A Framework to Implement Modern Neural Networks for Scientific Edge Computing. - G. Abarajithan; Zhenghua Ma; Zepeng Li; Shrideep Koparkar; Ravidu Munasinghe; Francesco Restuccia 002; Ryan Kastner (CoRR, 2024)

TOP: Towards Open & Predictable Heterogeneous SoCs. - Luca Valente; Francesco Restuccia 002; Davide Rossi; Ryan Kastner; Luca Benini (IEEE Trans. Computers, 2024)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. - Thomas Benz; Alessandro Ottaviano; Chaoqun Liang; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Davide Rossi; Luca Benini (IEEE Trans. Computers, 2025)