A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits. - Landon Caley; Chien-Wei Lo; Francis Sabado; Jia Di (ICICDT, 2014)

Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation. - Jean Pierre T. Habimana; Francis Sabado; Jia Di (ISCAS, 2016)

Recent Advances in Low Power Asynchronous Circuit Design. - Jia Di; Brent A. Bell; William Bouillon; John Brady; Thao Le 001; Chien-Wei Lo; Liang Men; Spencer Nelson; Francis Sabado; Andrew Suchanek (J. Low Power Electron., 2017)