A Power-Efficient High-Throughput 32-Thread SPARC Processor. - Ana Sonia Leon; Jinuk Luke Shin; Kenway W. Tam; William Bryg; Francis Schumacher; Poonacha Kongetira; David Weisner; Allan Strong (ISSCC, 2006)

A Power-Efficient High-Throughput 32-Thread SPARC Processor. - Ana Sonia Leon; Kenway W. Tam; Jinuk Luke Shin; David Weisner; Francis Schumacher (IEEE J. Solid State Circuits, 2007)

A 40nm 16-core 128-thread CMT SPARC SoC processor. - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith 002; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (ISSCC, 2010)

A 40 nm 16-Core 128-Thread SPARC SoC Processor. - Jinuk Luke Shin; Dawei Huang; Bruce Petrick; Changku Hwang; Kenway W. Tam; Alan P. Smith 002; Ha Pham; Hongping Penny Li; Timothy Johnson; Francis Schumacher; Ana Sonia Leon; Allan Strong (IEEE J. Solid State Circuits, 2011)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)