Reconfigurable Instruction Set Processors: A Survey. - Francisco Barat; Rudy Lauwereins (IEEE International Workshop on Rapid System Prototyping, 2000)

CRISP: A Template for Reconfigurable Instruction Set Processors. - Pieter Op de Beeck; Francisco Barat; Murali Jayapala; Rudy Lauwereins (FPL, 2001)

Bridging the Educational Gap in Embedded Systems Curricula: Developing an E-commerce Audio Streaming System. - Marc Leeman; Francisco Barat; Vincenzo De Florio; Geert Deconinck (ECBS, 2002)

A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. - Murali Jayapala; Francisco Barat; Pieter Op de Beeck; Francky Catthoor; Geert Deconinck; Henk Corporaal (PATMOS, 2002)

Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. - Francisco Barat; Murali Jayapala; Pieter Op de Beeck; Geert Deconinck (ASP-DAC/VLSI Design, 2002)

Reconfigurable Instruction Set Processors from a Hardware/Software Perspective. - Francisco Barat; Rudy Lauwereins; Geert Deconinck (IEEE Trans. Software Eng., 2002)

Low Power Coarse-Grained Reconfigurable Instruction Set Processor. - Francisco Barat; Murali Jayapala; Tom Vander Aa; Rudy Lauwereins; Geert Deconinck; Henk Corporaal (FPL, 2003)

Instruction buffering exploration for low energy VLIWs with instruction clusters. - Tom Vander Aa; Murali Jayapala; Francisco Barat; Geert Deconinck; Rudy Lauwereins; Francky Catthoor; Henk Corporaal (ASP-DAC, 2004)

L0 Cluster Synthesis and Operation Shuffling. - Murali Jayapala; Tom Vander Aa; Francisco Barat; Francky Catthoor; Henk Corporaal; Geert Deconinck (PATMOS, 2004)

Design Style Case Study for Embedded Multi Media Compute Nodes. - Andy Lambrechts; Tom Vander Aa; Murali Jayapala; Guillermo Talavera; Anthony Leroy; Adelina Shickova; Francisco Barat; Bingfeng Mei; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; et al. (RTSS, 2004)

L0 buffer energy optimization through scheduling and exploration. - Murali Jayapala; Tom Vander Aa; Francisco Barat; Geert Deconinck; Francky Catthoor; Henk Corporaal (SAC, 2004)

Instruction buffering exploration for low energy embedded processors. - Tom Vander Aa; Murali Jayapala; Francisco Barat; Geert Deconinck; Rudy Lauwereins; Henk Corporaal; Francky Catthoor (J. Embed. Comput., 2005)

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. - Murali Jayapala; Francisco Barat; Tom Vander Aa; Francky Catthoor; Henk Corporaal; Geert Deconinck (IEEE Trans. Computers, 2005)

A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V. - Maryam Ashouei; Jos Hulzink; Mario Konijnenburg; Jun Zhou 017; Filipa Duarte; Arjan Breeschoten; Jos Huisken; Jan Stuyt; Harmke de Groot; Francisco Barat; Johan David; Johan Van Ginderdeuren (ISSCC, 2011)

An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold. - Jos Hulzink; Mario Konijnenburg; Maryam Ashouei; Arjan Breeschoten; Torfinn Berset; Jos Huisken; Jan Stuyt; Harmke de Groot; Francisco Barat; Johan David; Johan Van Ginderdeuren (IEEE Trans. Biomed. Circuits Syst., 2011)

AMD XDNA NPU in Ryzen AI Processors. - Alejandro Rico; Satyaprakash Pareek; Javier Cabezas; David Clarke; Baris Özgül; Francisco Barat; Yao Fu; Stephan Münz; Dylan Stuart; Patrick Schlangen; Pedro Duarte; Sneha Date; et al. (IEEE Micro, 2024)