Fault attack on FPGA implementations of Trivium stream cipher. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (ISCAS, 2016)

Vulnerability Analysis of Trivium FPGA Implementations. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Carmen Baena Oliva; Pilar Parra Fernández; Manuel Valencia-Barrero (DCIS, 2018)

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Ricardo Chaves; Manuel Valencia-Barrero; Antonio Acosta-Jiménez; Carlos Jesús Jiménez-Fernández (ISCAS, 2020)

An Academic Approach to FPGA Design Based on a Distance Meter Circuit. - Carlos Jesús Jiménez-Fernández; Carmen Baena Oliva; Pilar Parra Fernández; Francisco Eugenio Potestad-Ordóñez; Manuel Valencia-Barrero (Rev. Iberoam. de Tecnol. del Aprendiz., 2020)

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Manuel Valencia-Barrero; Carmen Baena Oliva; Pilar Parra Fernández; Carlos Jesús Jiménez-Fernández (Sensors, 2020)

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (IEEE Access, 2021)

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (Sensors, 2021)

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Antonio J. Acosta 001; Carlos Jesús Jiménez-Fernández; Ricardo Chaves (IEEE Access, 2022)

Cryptographic Security Through a Hardware Root of Trust. - Luis F. Rojas-Muñoz; Santiago Sánchez-Solano; Macarena C. Martínez-Rodríguez; Eros Camacho-Ruiz; Pablo Navarro-Torrero; Apurba Karmakar; Carlos Fernández García; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Alejandro Casado-Galán; Pau Ortega-Castro; Antonio Acosta-Jiménez; et al. (ARC, 2024)

Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation. - Alejandro Casado-Galán; Francisco Eugenio Potestad-Ordóñez; Antonio J. Acosta 001; Erica Tena-Sánchez (DCIS, 2024)

Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Virginia Zúñiga-González; Antonio J. Acosta 001 (DSD, 2024)

Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs. - Francisco Eugenio Potestad-Ordóñez; Alejandro Casado-Galán; Erica Tena-Sánchez (Sensors, 2024)

TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF. - Alejandro Casado-Galán; J. Núñez-Martínez; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Antonio J. Acosta 001 (SMACD, 2025)