High-Speed RS(255, 239) Decoder Based on LCC Decoding. - Francisco Garcia-Herrero; Javier Valls; Pramod Kumar Meher (Circuits Syst. Signal Process., 2011)

Decoder for an enhanced serial generalized bit flipping algorithm. - Francisco Garcia-Herrero; María José Canet; Javier Valls (ICECS, 2012)

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Mark F. Flanagan (IEEE Commun. Lett., 2012)

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Low latency T-EMS decoder for non-binary LDPC codes. - Erbao Li; Francisco Garcia-Herrero; David Declercq; Kiran K. Gunnam; Jesus Omar Lacruz; Javier Valls (ACSSC, 2013)

High-speed NB-LDPC decoder for wireless applications. - Francisco Garcia-Herrero; Ma José Canet; Javier Valls (ISPACS, 2013)

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls (Circuits Syst. Signal Process., 2013)

A symbol flipping decoder for NB-LDPC relying on multiple votes. - Francisco Garcia-Herrero; David Declercq; Javier Valls (ISTC, 2014)

Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree. - J. M. Català-Pérez; Francisco Garcia-Herrero; Javier Valls; K. Liu; Shu Lin 001 (IEEE Commun. Lett., 2014)

Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes. - Francisco Garcia-Herrero; David Declercq; Javier Valls (IEEE Commun. Lett., 2014)

Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. - Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. - Francisco Garcia-Herrero; Erbao Li; David Declercq; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 630 Mbps non-binary LDPC decoder for FPGA. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Ma José Canet; Javier Valls; Asuncion Perez-Pascual (ISCAS, 2015)

One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Javier Valls-Coquillat; David Declercq (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. - Jesus Omar Lacruz; Francisco Garcia-Herrero; David Declercq; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2015)

High-Performance NB-LDPC Decoder With Reduction of Message Exchange. - Jesus Omar Lacruz; Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. - Jesus Omar Lacruz; Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2016)

High-Throughput One-Channel RS(255, 239) Decoder. - Gabriele Perrone; Javier Valls; Vicente Torres 001; Francisco Miguel Garcia-Herrero (DSD, 2018)

Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). - Vicente Torres 001; Javier Valls; María José Canet; Francisco Garcia-Herrero (NEWCAS, 2018)

Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. - J. M. Català-Pérez; Jesus Omar Lacruz; Francisco Garcia-Herrero; Javier Valls; David Declercq (Circuits Syst. Signal Process., 2019)

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. - Gabriele Perrone; Javier Valls; Vicente Torres 001; Francisco Garcia-Herrero (Circuits Syst. Signal Process., 2019)

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. - Javier Valls; Vicente Torres 001; María José Canet; Francisco Miguel Garcia-Herrero (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications. - Luis Alberto Aranda; Francisco Garcia-Herrero; Luis Esteban; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Access, 2020)

Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA. - Kyle W. Gear; Alfonso Sánchez-Macián; Francisco Garcia-Herrero; Juan Antonio Maestro (Circuits Syst. Signal Process., 2020)

Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase. - Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Circuits Syst., 2020)

Project-Based Learning with historic buildings: immersion in real training environments for the Degree in Technical Architecture. - David Villanueva Valentín-Gamazo; Neslon Tuesta Durango; Francisco Garcia-Herrero; M. Isabel Mansilla Blanco; M. Cruz Rey de las Moras (CINAIC, 2021)

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Access, 2021)

Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. - Javier Valls; Francisco Garcia-Herrero; Nithin Raveendran; Bane Vasic (IEEE Access, 2021)

Low delay non-binary error correction codes based on Orthogonal Latin Squares. - Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro (Integr., 2021)

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. - Oscar Ruano; Francisco Garcia-Herrero; Luis Alberto Aranda; Alfonso Sánchez-Macián; Laura Rodriguez; Juan Antonio Maestro (Sensors, 2021)

Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures. - Francisco Garcia-Herrero; Gary McGuire; Mark F. Flanagan; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories. - Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Emerg. Top. Comput., 2021)

Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. - Yao-Ming Kuo; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (Comput. Electr. Eng., 2022)

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale. - Alfonso Sánchez-Macián; Alonso Martín-Toledano; Jefferson Andres Bravo-Montes; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Trans. Emerg. Top. Comput., 2022)

Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. - Jefferson Andres Bravo-Montes; Alonso Martín-Toledano; Alfonso Sánchez-Macián; Oscar Ruano; Francisco Garcia-Herrero (J. Supercomput., 2022)

Layered Decoding of Quantum LDPC Codes. - Julien du Crest; Francisco Garcia-Herrero; Mehdi Mhalla; Valentin Savin; Javier Valls (ISTC, 2023)

RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. - Yao-Ming Kuo; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Computers, 2023)

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. - Yao-Ming Kuo; Mark F. Flanagan; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2023)

Low-Complexity Linear Programming Based Decoding of Quantum LDPC Codes. - Sana Javed; Francisco Garcia-Herrero; Bane Vasic; Mark F. Flanagan (ICC, 2024)

On the Use of Calibration Data in Error-Aware Compilation Techniques for NISQ Devices. - Handy Kurniawan; Laura Rodríguez-Soriano; Daniele Cuomo; Carmen G. Almudéver; Francisco Garcia-Herrero (QCE, 2024)

Noise-Aware Compilation Techniques for Enhanced Fault-Tolerant Preparation of Polar Code States. - Handy Kurniawan; Valentin Savin; Carmen G. Almudéver; Francisco Garcia-Herrero (QCE, 2024)

Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes. - Julien du Crest; Francisco Garcia-Herrero; Mehdi Mhalla; Valentin Savin; Javier Valls (Quantum, 2024)

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. - José Luis Imaña; Luis Piñuel; Yao-Ming Kuo; Oscar Ruano; Francisco Garcia-Herrero (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Implementing Quantum Polar Codes in a Superconducting Processor: From State Preparation to Decoding [Focus: Quantum Software and Its Engineering]. - Handy Kurniawan; Valentin Savin; Carmen G. Almudéver; Francisco Garcia-Herrero (IEEE Softw., 2025)

Predicting the Temporal Variability of Error Rates in Superconducting Quantum Processors: Mitigating Error Accuracy Loss in Queue-Based Quantum Computing Platforms [Focus: Quantum Software and its Engineering]. - Laura Rodríguez-Soriano; Francisco Garcia-Herrero; Carmen G. Almudéver (IEEE Softw., 2025)

Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications. - Daniel Báscones; Francisco Garcia-Herrero; Oscar Ruano; Carlos González 002; Daniel Mozos; Juan Antonio Maestro (IEEE Trans. Computers, 2025)