C-Switches: Increasing Switch Radix with Current Integration Scale. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco José Alfaro; José Duato (HPCC, 2011)

Self-related traces: An alternative to full-system simulation for NoCs. - Francisco Triviño; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; Alberto Ros 001 (HPCS, 2011)

Evaluation of an Alternative for Increasing Switch Radix. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco José Alfaro; José Duato (NCA, 2011)

Optimal Configuration of High-Radix Combined Switches. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco José Alfaro; José Duato (PDP, 2012)

Obtaining the optimal configuration of high-radix Combined switches. - Juan A. Villar; Francisco J. Andujar; José L. Sánchez 002; Francisco J. Alfaro; José A. Gámez 001; José Duato (J. Parallel Distributed Comput., 2013)

Deadlock-free routing mechanism for 3D twin torus networks. - Francisco J. Andújar; Juan A. Villar; Francisco J. Alfaro; José L. Sánchez 002; José Duato (INA-OCMC@HiPEAC, 2014)

Optimal Configuration for N-Dimensional Twin Torus Networks. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato (NCA, 2014)

Building 3D Torus Using Low-Profile Expansion Cards. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato (IEEE Trans. Computers, 2014)

Formalization and configuration methodology for high-radix combined switches. - Juan A. Villar; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; José Duato (J. Supercomput., 2014)

VEF Traces: A Framework for Modelling MPI Traffic in Interconnection Network Simulators. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; Jesús Escudero-Sahuquillo (CLUSTER, 2015)

N-Dimensional Twin Torus Topology. - Francisco J. Andujar-Munoz; Juan A. Villar-Ortiz; José L. Sánchez 002; Francisco José Alfaro; José Duato (IEEE Trans. Computers, 2015)

Optimizing the configuration of combined high-radix switches. - Juan A. Villar; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; José Duato (J. Supercomput., 2015)

Adaptive Routing for N-Dimensional Twin Torus. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato Marín (IEEE Trans. Computers, 2016)

An open-source family of tools to reproduce MPI-based workloads in interconnection network simulators. - Francisco J. Andujar; Juan A. Villar; Francisco J. Alfaro; José L. Sánchez 002; Jesús Escudero-Sahuquillo (J. Supercomput., 2016)

A Case Study on Implementing Virtual 5D Torus Networks Using Network Components of Lower Dimensionality. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato; Holger Fröning (HiPINEB@HPCA, 2017)

Applying search algorithms to obtain the optimal configuration of nDT torus nodes. - Francisco J. Andujar-Munoz; Juan A. Villar-Ortiz; José Luis Sánchez Garcia; Francisco J. Alfaro-Cortes (Concurr. Comput. Pract. Exp., 2017)

Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes. - Francisco J. Andujar; Salvador Coll; Marina Alonso; Juan-Miguel Martínez 001; Pedro López 001; Francisco J. Alfaro; José L. Sánchez 002; Raúl Martínez (HiPINEB@HPCA, 2018)

VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems. - Javier Cano-Cano; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002 (HiPINEB@HPCA, 2018)

Constructing virtual 5-dimensional tori out of lower-dimensional network cards. - Francisco J. Andujar; Juan A. Villar; José L. Sánchez 002; Francisco J. Alfaro; José Duato; Holger Fröning (Concurr. Comput. Pract. Exp., 2019)

Energy efficient torus networks with on/off links. - Francisco J. Andújar; Salvador Coll; Marina Alonso; Juan-Miguel Martínez 001; Pedro López 001; José L. Sánchez 002; Francisco J. Alfaro; Raúl Martínez (J. Parallel Distributed Comput., 2019)

Speeding up exascale interconnection network simulations with the VEF3 trace framework. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro; José L. Sánchez 002 (J. Parallel Distributed Comput., 2019)

POWAR: Power-Aware Routing in HPC Networks with On/Off Links. - Francisco J. Andújar; Salvador Coll; Marina Alonso; Pedro López 001; Juan-Miguel Martínez 001 (ACM Trans. Archit. Code Optim., 2019)

QoS provision in hierarchical and non-hierarchical switch architectures. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro-Cortés; José L. Sánchez 002 (J. Parallel Distributed Comput., 2021)

A methodology to enable QoS provision on InfiniBand hardware. - Javier Cano-Cano; Francisco J. Andújar; Jesús Escudero-Sahuquillo; Francisco J. Alfaro-Cortés; José L. Sánchez 002 (J. Supercomput., 2021)

Efficient heterogeneous programming with FPGAs using the Controller model. - Gabriel Rodriguez-Canal; Yuri Torres; Francisco J. Andújar; Arturo González-Escribano (J. Supercomput., 2021)

Enabling Quality of Service Provision in Omni-Path Switches. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro-Cortés; José L. Sánchez 002 (Comput. Math. Methods, 2021)

Providing quality of service in omni-path networks. - Javier Cano-Cano; Francisco J. Andújar; Francisco J. Alfaro-Cortés; José L. Sánchez 002; Gaspar Mora (J. Supercomput., 2022)

Open SYCL on heterogeneous GPU systems: A case of study. - Rocío Carratalá-Sáez; Francisco J. Andújar; Yuri Torres; Arturo González-Escribano; Diego R. Llanos (CoRR, 2023)

Energy efficient HPC network topologies with on/off links. - Francisco J. Andújar; Salvador Coll; Marina Alonso; Juan-Miguel Martínez 001; Pedro López 001; José L. Sánchez 002; Francisco J. Alfaro (Future Gener. Comput. Syst., 2023)

Extending the VEF traces framework to model data center network workloads. - Francisco J. Andújar; Miguel Sánchez de la Rosa; Jesús Escudero-Sahuquillo; José L. Sánchez 002 (J. Supercomput., 2023)

Supporting efficient overlapping of host-device operations for heterogeneous programming with CtrlEvents. - Yuri Torres; Francisco J. Andújar; Arturo González-Escribano; Diego R. Llanos (J. Parallel Distributed Comput., 2023)

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. - Manuel de Castro; Roberto R. Osorio; Francisco J. Andújar; Rocío Carratalá-Sáez; Yuri Torres; Diego R. Llanos (Euro-Par Workshops (1), 2024)

Quality-of-Service Provision for BXI3-Based Interconnection Networks. - Miguel Sánchez de la Rosa; Gabriel Gomez-Lopez; Francisco J. Andújar; Jesús Escudero-Sahuquillo; José L. Sánchez 002; Francisco J. Alfaro; Pierre-Axel Lagadec (HOTI, 2024)

Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools. - Manuel de Castro; Roberto R. Osorio; Francisco J. Andujar; Rocío Carratalá-Sáez; Yuri Torres; Diego R. Llanos (CoRR, 2024)

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. - Manuel de Castro; Francisco J. Andújar; Roberto R. Osorio; Rocío Carratalá-Sáez; Diego R. Llanos (CoRR, 2024)

Applying machine learning to assess emotional reactions to video game content streamed on Spanish Twitch channels. - Noemí Merayo; Rosalía Cotelo; Rocío Carratalá-Sáez; Francisco J. Andújar (Comput. Speech Lang., 2024)

Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application. - Manuel de Castro; Roberto R. Osorio; Francisco J. Andújar; Rocío Carratalá-Sáez; Yuri Torres; Diego R. Llanos (IEEE Access, 2025)

Quality-of-service provision for BXIv3-based interconnection networks. - Miguel Sánchez de la Rosa; Gabriel Gomez-Lopez; Francisco J. Andújar; Jesús Escudero-Sahuquillo; José L. Sánchez 002; Francisco J. Alfaro-Cortés; Pierre-Axel Lagadec (J. Supercomput., 2025)