Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. - Bingfeng Mei; Francisco-Javier Veredas; Bart Masschelein (FPL, 2005)

Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. - Francisco-Javier Veredas; Michael Scheppler; Will Moffat; Bingfeng Mei (FPL, 2005)

Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. - Francisco-Javier Veredas; Jordi Carrabina (PATMOS, 2005)

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. - Francisco-Javier Veredas; Michael Scheppler; Hans-Jörg Pfleiderer (DATE Designers' Forum, 2006)

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. - Francisco-Javier Veredas; Hans-Jörg Pfleiderer (FPL, 2006)

Power estimation of a LUT-based MPGA. - Francisco-Javier Veredas; Hans-Jörg Pfleiderer (FPT, 2006)

LUT-based MPGAs for fast turnaround time conversion flow. - Francisco-Javier Veredas; Michael Scheppler; Bumei Zhai; Hans-Jörg Pfleiderer (ISCAS, 2006)

Regular Routing Architecture for a LUT-based MPGA. - Francisco-Javier Veredas; Michael Scheppler; Bumei Zhai; Hans-Jörg Pfleiderer (ISVLSI, 2006)

FPGA Placement Improvement Using a Genetic Algorithm and the Routing Algorithm as a Cost Function. - Francisco-Javier Veredas; Enrique J. Carmona (DSD, 2018)