Dependability Evaluation of Fault Tolerant Distributed Industrial Control Systems. - José Carlos Campelo; Pedro Yuste; Francisco Rodríguez 003; Pedro J. Gil; Juan José Serrano (IPPS/SPDP Workshops, 1999)

Hierarchical Reliability and Safety Models of Fault Tolerant Distributed Industrial Control Systems. - José Carlos Campelo; Pedro Yuste; Francisco Rodríguez 003; Pedro J. Gil; Juan José Serrano (SAFECOMP, 1999)

Design and Validation of a Distributed Industrial Control System's Nodes. - José Carlos Campelo; Francisco Rodríguez 003; Pedro J. Gil; Juan José Serrano (SRDS, 1999)

Distributed industrial control systems: a fault-tolerant architecture. - José Carlos Campelo; Francisco Rodríguez 003; Alicia Rubio; Rafael Ors; Pedro J. Gil; Lenin Lemus; J. V. Busquets; José Albaladejo; Juan José Serrano (Microprocess. Microsystems, 1999)

A Memory Overhead valuation of the Interleaved Signature Instruction Stream. - Francisco Rodríguez 003; José Carlos Campelo; Juan José Serrano (DFT, 2002)

Delivering error detection capabilities into a field programmable device: the HORUS processor case study. - Francisco Rodríguez 003; José Carlos Campelo; Juan José Serrano (FPT, 2002)

A Watchdog Processor Architecture with Minimal Performance Overhead. - Francisco Rodríguez 003; José Carlos Campelo; Juan José Serrano (SAFECOMP, 2002)

Tuning Genetic Algorithms for Real Time Systems Using a Grid. - Antonio Martí Campoy; Francisco Rodríguez 003; Angel Perles Ivars (PDCAT, 2004)

Experiences on Parallel Replicated Discrete-Event Simulation on a GRID. - Angel Perles Ivars; Antonio Martí Campoy; Francisco Rodríguez 003; Juan José Serrano; Miguel A. Mateo Pla (GCC, 2005)

On Using Locking Caches in Embedded Real-Time Systems. - Antonio Martí Campoy; Eugenio Tamura; Sergio Sáez; Francisco Rodríguez 003; José V. Busquets-Mataix (ICESS, 2005)

Control Flow Error Checking with ISIS. - Francisco Rodríguez 003; Juan José Serrano (ICESS, 2005)

Saving Cache Memory Using a Locking Cache in Real-time Systems. - Antonio Martí Campoy; Francisco Rodríguez-Ballester; Rafael Ors; Juan José Serrano (CDES, 2009)

Parallel Implementation of a Genetic Algorithm Using a Grid. - Antonio Martí Campoy; Eugenio Tamura; Francisco Rodríguez-Ballester; Juan José Serrano (GCA, 2009)

An algorithm for deciding minimal cache sizes in real-time systems. - Antonio Martí Campoy; Francisco Rodríguez-Ballester; Eugenio Tamura Morimitsu; Rafael Ors (GECCO, 2011)

Efficient Wavelet Sign Prediction: Simulated Annealing vs Genetic Algorithms. - J. M. Navarro; Pedro Moreno-Bernal; Francisco Rodríguez-Ballester; Antonio Martí Campoy; Marco Antonio Cruz-Chavez; Manuel P. Malumbres; Otoniel López (KES, 2012)

Using Dynamic, Full Cache Locking and Genetic Algorithms for Cache Size Minimization in Multitasking, Preemptive, Real-Time Systems. - Antonio Martí Campoy; Francisco Rodríguez-Ballester; Rafael Ors Carot (TPNC, 2013)

Applying a Genetic Algorithm Solution to Improve Compression of Wavelet Coefficient Sign. - Antonio Martí Campoy; Otoniel López; Francisco Rodríguez-Ballester; Manuel P. Malumbres (IWANN (1), 2015)

Design of a Computerised Flight Mill Device to Measure the Flight Potential of Different Insects. - Antonio Martí Campoy; Juan Antonio Ávalos; Antonia Soto; Francisco Rodríguez-Ballester; Victoria Martínez-Blay; Manuel P. Malumbres (Sensors, 2016)

Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems. - Antonio Martí Campoy; Francisco Rodríguez-Ballester (ETFA, 2019)