Francisco Rodríguez

Orcid: 0000-0002-4087-5077

Affiliations:
  • Technical University of Valencia, Department of Computer Engineering, Spain


According to our database1, Francisco Rodríguez authored at least 19 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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Bibliography

2019
Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019

2016
Design of a Computerised Flight Mill Device to Measure the Flight Potential of Different Insects.
Sensors, 2016

2015
Applying a Genetic Algorithm Solution to Improve Compression of Wavelet Coefficient Sign.
Proceedings of the Advances in Computational Intelligence, 2015

2013
Using Dynamic, Full Cache Locking and Genetic Algorithms for Cache Size Minimization in Multitasking, Preemptive, Real-Time Systems.
Proceedings of the Theory and Practice of Natural Computing, 2013

2012
Efficient Wavelet Sign Prediction: Simulated Annealing vs Genetic Algorithms.
Proceedings of the Advances in Knowledge-Based and Intelligent Information and Engineering Systems, 2012

2011
An algorithm for deciding minimal cache sizes in real-time systems.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

2009
Parallel Implementation of a Genetic Algorithm Using a Grid.
Proceedings of the 2009 International Conference on Grid Computing & Applications, 2009

Saving Cache Memory Using a Locking Cache in Real-time Systems.
Proceedings of the 2009 International Conference on Computer Design, 2009

2005
Control Flow Error Checking with ISIS.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

On Using Locking Caches in Embedded Real-Time Systems.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Experiences on Parallel Replicated Discrete-Event Simulation on a GRID.
Proceedings of the Grid and Cooperative Computing - GCC 2005, 4th International Conference, Beijing, China, November 30, 2005

2004
Tuning Genetic Algorithms for Real Time Systems Using a Grid.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004

2002
A Watchdog Processor Architecture with Minimal Performance Overhead.
Proceedings of the Computer Safety, 2002

Delivering error detection capabilities into a field programmable device: the HORUS processor case study.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

A Memory Overhead valuation of the Interleaved Signature Instruction Stream.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

1999
Distributed industrial control systems: a fault-tolerant architecture.
Microprocess. Microsystems, 1999

Design and Validation of a Distributed Industrial Control System's Nodes.
Proceedings of the Eighteenth Symposium on Reliable Distributed Systems, 1999

Hierarchical Reliability and Safety Models of Fault Tolerant Distributed Industrial Control Systems.
Proceedings of the Computer Safety, 1999

Dependability Evaluation of Fault Tolerant Distributed Industrial Control Systems.
Proceedings of the Parallel and Distributed Processing, 1999


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