Challenges and opportunity in performance, variability and reliability in sub-45 nm CMOS technologies. - Franck Arnaud; L. Pinzelli; C. Gallon; M. Rafik; P. Mora; Frédéric Boeuf (Microelectron. Reliab., 2011)

Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs. - Christoforos G. Theodorou; Eleftherios G. Ioannidis; Sébastien Haendler; Nicolas Planes; Franck Arnaud; Jalal Jomaah; Charalambos A. Dimitriadis; Gérard Ghibaudo (ESSDERC, 2012)

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. - Philippe Flatresse; Bastien Giraud; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Fabien Giner; Deepak-Kumar Arora; Franck Arnaud; Nicolas Planes; Julien Le Coz; Olivier Thomas; Sylvain Engels; Giorgio Cesana; et al. (ISSCC, 2013)

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. - François Andrieu; Mikaël Cassé; E. Baylac; P. Perreau; O. Nier; Denis Rideau; R. Berthelon; Franck Pourchon; A. Pofelski; Barbara De Salvo; C. Gallon; Vincent Mazzocchi; et al. (ESSDERC, 2014)

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. - David Jacquet; Frederic Hasbani; Philippe Flatresse; Robin Wilson; Franck Arnaud; Giorgio Cesana; Thierry Di Gilio; Christophe Lecocq; Tanmoy Roy; Amit Chhabra; Chiranjeev Grover; Olivier Minez; et al. (IEEE J. Solid State Circuits, 2014)

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. - Rossella Ranica; Nicolas Planes; Vincent Huard; Olivier Weber; Daniel Noblet; Damien Croain; Fabien Giner; Sylvie Naudet; P. Mergault; S. Ibars; A. Villaret; Maryline Parra; et al. (VLSI Circuits, 2016)

28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. - Franck Arnaud; Sébastien Haendler; Sylvain Clerc; Rossella Ranica; Anna Gandolfo; Olivier Weber (ESSDERC, 2019)

Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI. - Fabio Disegni; Roberto Annunziata; A. Molgora; G. Campardo; Paolo Cappelletti; P. Zuliani; P. Ferreira; A. Ventre; G. Castagna; Andreia Cathelin; Anna Gandolfo; F. Goller; et al. (VLSI Circuits, 2019)

Artificial Intelligence: Why moving it to the Edge? - Joël Hartmann; Paolo Cappelletti; Nitin Chawla; Franck Arnaud; Andreia Cathelin (ESSDERC, 2021)

Improving Ge-rich GST ePCM reliability through BEOL engineering. - Andrea Redaelli; Anna Gandolfo; Giulia Samanni; Enrico Gomiero; Elisa Petroni; Luca Scotti; Andrea Lippiello; Paolo Mattavelli; J. Jasse; D. Codegoni; A. Serafini; Rossella Ranica; et al. (ESSDERC, 2021)

16MB High Density Embedded PCM macrocell for automotive-grade microcontroller in 28nm FD-SOI, featuring extension to 24MB for Over-The-Air software update. - Fabio Disegni; A. Ventre; A. Molgora; Paolo Cappelletti; R. Badalamenti; P. Ferreira; G. Castagna; Andreia Cathelin; Anna Gandolfo; Andrea Redaelli; D. Manfrè; Alfonso Maurelli; et al. (VLSI Circuits, 2021)

An 18nm ePCM with BJT selector NVM design for advanced microcontroller applications. - Antonino Conte; Francesco Tomaiuolo; Marco Ruta; Andrea Redaelli; Franck Arnaud; Thomas Jouanneau; Christian Boccaccio; Olivier Weber (IMW, 2023)

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. - Joao Henrique Quintino Palhares; Yann Beilliard; Jury Sandrini; Franck Arnaud; Kevin Garello; Guillaume Prenat; Lorena Anghel; Fabien Alibart; Dominique Drouin; Philippe Galy (CoRR, 2023)

Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration. - R. Berthelon; Olivier Weber; F. Ibars; B. Revel; C. Borowiak; J. C. Grenier; B. Dumont; S. Desmoulins; P. O. Sassoulas; P. Ferreira; S. Chouteau; S. Niel; et al. (VLSI Technology and Circuits, 2024)