Concrete Impact of Formal Verification on Quality in IP Design and Implementation. - Umberto Rossi; Andrea Fedeli; Marco Boschini; Franco Toto (ISQED, 2001)

An error simulation based approach to measure error coverage of formal properties. - Paolo Azzoni; Andrea Fedeli; Franco Fummi; Graziano Pravadelli; Umberto Rossi; Franco Toto (ACM Great Lakes Symposium on VLSI, 2002)

A 1000X speed up for properties completeness evaluation. - A. Castelnuovo; Andrea Fedeli; Alessandro Fin; Franco Fummi; Graziano Pravadelli; Umberto Rossi; F. Sforza; Franco Toto (HLDVT, 2002)

On the Use of a High-Level Fault Model to Check Properties Incompleteness. - Franco Fummi; Graziano Pravadelli; Andrea Fedeli; Umberto Rossi; Franco Toto (MEMOCODE, 2003)

Coverage of formal properties based on a high-level fault model and functional ATPG. - Franco Fummi; Graziano Pravadelli; Franco Toto (ETS, 2005)