Contribution à l'étude de systèmes hiérarchisés de ressources dans l'architecture des machines informatiques. - François Anceau (1974)

Formal Verification: A Significant Step Towards Zero Deffect VLSI Design. - François Anceau (IFIP Congress, 1989)

FPGA implementation of reconfigurable ADPLL network for distributed clock generation. - Chuan Shan; Eldar Zianbetov; Mohammad Javidan; François Anceau; Mehdi Terosiet; Sylvain Feruglio; Dimitri Galayko; Olivier Romain; Éric Colinet; Jérôme Juillard (FPT, 2011)

A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors. - Mohammad Javidan; Eldar Zianbetov; François Anceau; Dimitri Galayko; Éric Colinet; Jérôme Juillard (ISCAS, 2011)

All-digital PLL array provides reliable distributed clock for SOCs. - Mohammad Javidan; Eldar Zianbetov; François Anceau; Dimitri Galayko; Anton Korniienko; Éric Colinet; Gérard Scorletti; Jean-Michel Akre; Jérôme Juillard (ISCAS, 2011)

A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. - Eldar Zianbetov; François Anceau; Mohammad Javidan; Dimitri Galayko; Éric Colinet; Jérôme Juillard (ISCAS, 2011)

Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. - Chuan Shan; Dimitri Galayko; François Anceau (NEWCAS, 2012)

Distributed clock generator for synchronous SoC using ADPLL network. - Eldar Zianbetov; Dimitri Galayko; François Anceau; Mohammad Javidan; Chuan Shan; Olivier Billoint; Anton Korniienko; Éric Colinet; Gérard Scorletti; J. M. Akrea; Jérôme Juillard (CICC, 2013)

On-chip clock error characterization for clock distribution system. - Chuan Shan; Dimitri Galayko; François Anceau (ISVLSI, 2013)

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. - Chuan Shan; Eldar Zianbetov; Weiqiang Yu; François Anceau; Olivier Billoint; Dimitri Galayko (ReConFig, 2013)

Complexity in heterogeneous systems on chips: Dsign and analysis challenges. - Dimitri Galayko; Elena Blokhina; Eldar Zianbetov; Andrii Dudka; François Anceau; Éric Colinet; Anton Korniienko; Jérôme Juillard; Philippe Basset (ISCAS, 2014)

"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. - Chuan Shan; François Anceau; Dimitri Galayko; Eldar Zianbetov (ISCAS, 2014)

A reconfigurable distributed architecture for clock generation in large many-core SoC. - Chuan Shan; Dimitri Galayko; François Anceau; Eldar Zianbetov (ReCoSoC, 2014)

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. - Chuan Shan; Eldar Zianbetov; François Anceau; Olivier Billoint; Dimitri Galayko (NEWCAS, 2015)

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. - Dimitri Galayko; Chuan Shan; Eldar Zianbetov; Mohammad Javidan; Anton Korniienko; François Anceau; Olivier Billoint; Éric Colinet; Elena Blokhina; Jérôme Juillard (IEEE Trans. Circuits Syst. II Express Briefs, 2019)