Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. - Alex Park 002; Venkat Narayanan; Keith A. Bowman; Francois Atallah; Alain Artieri; Sei Seung Yoon; Kendrick Yuen; David Hansquine (CICC, 2014)

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. - Keith A. Bowman; Alex Park 002; Venkat Narayanan; Francois Atallah; Alain Artieri; Sei Seung Yoon; Kendrick Yuen; David Hansquine (ITC, 2014)

A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. - Jihoon Jeong; Francois Atallah; Hoan Nguyen; Josh Puckett; Keith A. Bowman; David Hansquine (CICC, 2015)

8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. - Keith A. Bowman; Sarthak Raina; Todd Bridges; Daniel Yingling; Hoan Nguyen; Brad Appel; Yesh Kolla; Jihoon Jeong; Francois Atallah; David Hansquine (ISSCC, 2015)

Adaptive power gating of 32-bit Kogge Stone adder. - Alexander E. Shapiro; Francois Atallah; Kyugseok Kim; Jihoon Jeong; Jeff Fischer; Eby G. Friedman (Integr., 2016)

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. - Keith A. Bowman; Sarthak Raina; Todd Bridges; Daniel Yingling; Hoan Nguyen; Brad Appel; Yesh Kolla; Jihoon Jeong; Francois Atallah; David Hansquine (IEEE J. Solid State Circuits, 2016)

Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. - Samantak Gangopadhyay; Saad Bin Nasir; Hoan Nguyen; Jihoon Jeong; Francois Atallah; Keith A. Bowman; Arijit Raychowdhury (CICC, 2017)

A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. - Hoan Nguyen; Jihoon Jeong; Francois Atallah; Marc Jansen; Anthony Polomik; Daniel Yingling; Harsha Akkaraju; Brad Appel; Rahul Nadkarni; Keith A. Bowman (VLSI Circuits, 2018)

A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. - Francois Atallah; Keith A. Bowman; Hoan Nguyen; Jihoon Jeong; Daniel Yingling; Yu Sun; Brad Appel; Anthony Polomik; Mahesh Harinath; Joshua Morelli; Thomas Moore; Nathaniel Reeves; et al. (ISSCC, 2019)

A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. - Keith A. Bowman; Samantak Gangopadhyay; Francois Atallah; Hoan Nguyen; Jihoon Jeong; Daniel Yingling; Anthony Polomik; Mahesh Harinath; Nathaniel Reeves; Amer Cassier; Brad Appel; Arijit Raychowdhury (VLSI Circuits, 2019)