Development of a permittivity extraction method for ultra low k dielectrics integrated in advanced interconnects. - Olga Cueto; Myriam Assous; François de Crecy; A. Toffoli; David Bouchu; M. Fayolle; Frédéric Boulanger (Microelectron. Reliab., 2007)

An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling. - Léa Di Cioccio; Pierric Gueguen; Rachid Taibi; Thomas Signamarcheix; Laurent Bally; Laurent Vandroux; Marc Zussy; Sophie Verrun; Jérôme Dechamp; Patrick Leduc; Myriam Assous; David Bouchu; et al. (3DIC, 2009)

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. - Sylvain Joblot; Alexis Farcy; Nicolas Hotellier; Amadine Jouve; François de Crecy; Arnaud Garnier; M. Argoud; C. Ferrandon; J.-P. Colonna; R. Franiatte; C. Laviron; Séverine Cheramy (3DIC, 2013)

Thermal correlation between measurements and FEM simulations in 3D ICs. - Papa Momar Souare; François de Crecy; Vincent Fiori; M. Haykel Ben Jamaa; Alexis Farcy; Sébastien Gallois-Garreignot; Andras Borbely; Jean-Philippe Colonna; Perceval Coudrain; B. Giraud; C. Laviron; Séverine Cheramy; et al. (3DIC, 2013)

Using TSVs for thermal mitigation in 3D circuits: Wish and truth. - Cristiano Santos; Papa Momar Souare; François de Crecy; Perceval Coudrain; Jean-Philippe Colonna; Pascal Vivet; Andras Borbely; Ricardo Reis 001; M. Haykel Ben Jamaa; Vincent Fiori; Alexis Farcy (3DIC, 2014)

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. - Perceval Coudrain; Papa Momar Souare; Rafael Prieto; Vincent Fiori; Alexis Farcy; Laurent Le Pailleur; Jean-Philippe Colonna; Cristiano Santos; Pascal Vivet; M. Haykel Ben Jamaa; Denis Dutoit; François de Crecy; et al. (IEEE Des. Test, 2016)