Optimal design of synchronous circuits using software pipelining techniques. - François R. Boyer; El Mostapha Aboulhamid; Yvon Savaria; Imed Eddine Bennour (ICCD, 1998)

An efficient verification method for a class of multi-phase sequential circuits. - François-Raymond Boyer; El Mostapha Aboulhamid; Yvon Savaria (ICECS, 2000)

Optimal design of synchronous circuits using software pipelining techniques. - François R. Boyer; El Mostapha Aboulhamid; Yvon Savaria; Michel Boyer (ACM Trans. Design Autom. Electr. Syst., 2001)

SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. - Jérôme Chevalier; Mathieu Rondonneau; Olivier Benny; Guy Bois; El Mostapha Aboulhamid; François R. Boyer (FDL, 2003)

.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. - James Lapalme; El Mostapha Aboulhamid; Gabriela Nicolescu; Luc Charest; François R. Boyer; J. P. David; Guy Bois (DATE, 2004)

ESys.Net: a new solution for embedded systems modeling and simulation. - James Lapalme; El Mostapha Aboulhamid; Gabriela Nicolescu; Luc Charest; François R. Boyer; J. P. David; Guy Bois (LCTES, 2004)

Implementation of a cycle by cycle variable speed processor. - H. G. Epassa; François R. Boyer; Yvon Savaria (ISCAS (4), 2005)

Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. - Bill Pontikakis; François R. Boyer; Yvon Savaria (IWSOC, 2005)

A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. - Bill Pontikakis; François R. Boyer; Yvon Savaria (ISCAS, 2006)

Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. - Abdelaziz Trabelsi; François-Raymond Boyer; Yvon Savaria; Mounir Boukadoum (ICECS, 2007)

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. - Bill Pontikakis; Hung Tien Bui; François R. Boyer; Yvon Savaria (ISCAS, 2007)

Robust estimation of LP parameters in white noise with unknown variance. - Abdelaziz Trabelsi; Mounir Boukadoum; François-Raymond Boyer (ICECS, 2009)

Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). - Marcel Siadjine Njinowa; Hung Tien Bui; François R. Boyer (ISCAS, 2010)

Design of low power 4-bit flash ADC based on standard cells. - Marcel Siadjine Njinowa; Hung Tien Bui; François-Raymond Boyer (NEWCAS, 2013)

Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. - Alexsandre B. Lacroix; J. M. Pierre Langlois; François-Raymond Boyer; Antoine Gosselin; Guy Bois (ANCS, 2016)

Performance characterization of an SCMA decoder. - Roya Alizadeh; Normand Bélanger; Yvon Savaria; François R. Boyer (NEWCAS, 2016)

A fast systolic priority queue architecture for a flow-based Traffic Manager. - Imad Benacer; François-Raymond Boyer; Normand Bélanger; Yvon Savaria (NEWCAS, 2016)

Extern Objects in P4: an ROHC Compression Case Study. - Jeferson Santiago da Silva; François-Raymond Boyer; Laurent-Olivier Chiquette; J. M. Pierre Langlois (CoRR, 2016)

A high-speed traffic manager architecture for flow-based networking. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (NEWCAS, 2017)

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. - Jeferson Santiago da Silva; François-Raymond Boyer; J. M. Pierre Langlois (FPGA, 2018)

Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (ISCAS, 2018)

Extern Objects in P4: an ROHC Header Compression Scheme Case Study. - Jeferson Santiago da Silva; François-Raymond Boyer; Laurent-Olivier Chiquette; J. M. Pierre Langlois (NetSoft, 2018)

HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (NEWCAS, 2018)

A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. - Jeferson Santiago da Silva; François-Raymond Boyer; J. M. Pierre Langlois (FCCM, 2019)

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2019)

HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. - Imad Benacer; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2019)

5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588. - Atabak Nojavan; Bill Pontikakis; François-Raymond Boyer; Yvon Savaria (IEEE Access, 2025)

P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. - Mohsen Rahmati; François-Raymond Boyer; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2025)