A Practical Approach to Static Signal Electromigration Analysis. - N. S. Nagaraj; Frank Cano; Haldun Haznedar; Duane Young (DAC, 1998)

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. - Lun Ye; Foong-Charn Chang; Peter Feldmann; Rakesh Chadha; Nagaraj Ns; Frank Cano (DATE, 1999)

Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. - Nagaraj Ns; Frank Cano; Sudha Thiruvengadam; Deepak Kapoor (ICCD, 1999)

Enabling DIR(Designing-In-Reliability) through CAD Capabilities. - Wonjae L. Kang; Brad Potts; Ray Hokinson; John Riley; David Doman; Frank Cano; N. S. Nagaraj; Noel Durrant (ISQED, 2000)

A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs. - N. S. Nagaraj; Frank Cano; Duane Young; Deepak Vohra; Manoj Das (VLSI Design, 2000)

Benchmarks for Interconnect Parasitic Resistance and Capacitance. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Frank Cano; Usha Narasimha; Mak Kulkarni; Poras T. Balsara; Cyrus D. Cantrell (ISQED, 2003)

Asymmetric aging of clock networks in power efficient designs. - Senthil Arasu; Mehrdad Nourani; Frank Cano; John M. Carulli; Vijay Reddy (ISQED, 2014)

Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs. - Palkesh Jain; Frank Cano; Bapana Pudi; N. V. Arvind (IEEE Trans. Very Large Scale Integr. Syst., 2014)

2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. - Rama Venkatasubramanian; Don Steiss; Greg Shurtz; Tim Anderson; Kai Chirca; Raghavendra Santhanagopal; Niraj Nandan; Anish Reghunath; Hetul Sanghvi; Daniel Wu; Abhijeet Chachad; Brian Karguth; et al. (ISSCC, 2020)