Optimal analog trim techniques for improving the linearity of pipeline ADCs. - Turker Kuyel; Frank (Ching-Yuh) Tsay (ITC, 2000)

A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply. - Yong-In Park; Soundarapandian Karthikeyan; Frank (Ching-Yuh) Tsay; Eduardo Bartolome (ISCAS (1), 2001)

Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters. - Alfio Zanchi; Ioannis Papantonopoulos; Frank (Ching-Yuh) Tsay (ISCAS (5), 2003)

Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS. - Alfio Zanchi; Frank (Ching-Yuh) Tsay; Ioannis Papantonopoulos (IEEE J. Solid State Circuits, 2003)

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter. - Alfio Zanchi; Frank (Ching-Yuh) Tsay (IEEE J. Solid State Circuits, 2005)