Design Space Exploration for Massively Parallel Processor Arrays. - Frank Hannig; Jürgen Teich (PaCT, 2001)

Generation of Distributed Loop Control. - Marcus Bednara; Frank Hannig; Jürgen Teich (Embedded Processor Design Challenges, 2002)

Energy estimation of nested loop programs. - Frank Hannig; Jürgen Teich (SPAA, 2002)

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. - Frank Hannig; Jürgen Teich (ASAP, 2004)

Regular mapping for coarse-grained reconfigurable architectures. - Frank Hannig; Hritam Dutta; Jürgen Teich (ICASSP (5), 2004)

Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. - Frank Hannig; Hritam Dutta; Jürgen Teich (IPDPS, 2004)

Dynamic Piecewise Linear/Regular Algorithms. - Frank Hannig; Jürgen Teich (PARELEC, 2004)

High-Speed Event-Driven RTL Compiled Simulation. - Alexey Kupriyanov; Frank Hannig; Jürgen Teich (SAMOS, 2004)

Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. - Thomas Schlichter; Christian Haubelt; Frank Hannig; Jürgen Teich (ASAP, 2005)

Output Serialization for FPGA-based and Coarse-grained Processor Arrays. - Frank Hannig; Jürgen Teich (ERSA, 2005)

Defragmenting the Module Layout of a Partially Reconfigurable Device. - Jan van der Veen; Sándor P. Fekete; Mateusz Majer; Ali Ahmadinia; Christophe Bobda; Frank Hannig; Jürgen Teich (ERSA, 2005)

Co-Design of Massively Parallel Embedded Processor Architectures. - Frank Hannig; Hritam Dutta; Alexey Kupriyanov; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Ronan Keryell; Bernard Pottier; Daniel Chillet; Daniel Ménard; Olivier Sentieys (ReCoSoC, 2005)

Automatic FIR Filter Generation for FPGAs. - Holger Ruckdeschel; Hritam Dutta; Frank Hannig; Jürgen Teich (SAMOS, 2005)

Defragmenting the Module Layout of a Partially Reconfigurable Device - Jan van der Veen; Sándor P. Fekete; Ali Ahmadinia; Christophe Bobda; Frank Hannig; Jürgen Teich (CoRR, 2005)

Controller Synthesis for Mapping Partitioned Programs on Array Architectures. - Hritam Dutta; Frank Hannig; Jürgen Teich (ARCS, 2006)

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. - Hritam Dutta; Frank Hannig; Jürgen Teich; Benno Heigl; Heinz Hornegger (ASAP, 2006)

A Generic Framework for Rapid Prototyping of System-on-Chip Designs. - Dmitrij Kissler; Alexey Kupriyanov; Frank Hannig; Dirk Koch; Jürgen Teich (CDES, 2006)

A highly parameterizable parallel processor array architecture. - Dmitrij Kissler; Frank Hannig; Alexey Kupriyanov; Jürgen Teich (FPT, 2006)

Hardware Cost Analysis for Weakly Programmable Processor Arrays. - Dmitrij Kissler; Frank Hannig; Alexey Kupriyanov; Jürgen Teich (SoC, 2006)

An Architecture Description Language for Massively Parallel Processor Architectures. - Alexey Kupriyanov; Frank Hannig; Dmitrij Kissler; Jürgen Teich; Rainer Schaffer; Renate Merker (MBMV, 2006)

Hierarchical Partitioning for Piecewise Linear Algorithms. - Hritam Dutta; Frank Hannig; Jürgen Teich (PARELEC, 2006)

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. - Dmitrij Kissler; Frank Hannig; Alexey Kupriyanov; Jürgen Teich (ReCoSoC, 2006)

Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. - Frank Hannig; Hritam Dutta; Jürgen Teich (Int. J. Embed. Syst., 2006)

Modeling of Interconnection Networks in Massively Parallel Processor Architectures. - Alexey Kupriyanov; Frank Hannig; Dmitrij Kissler; Jürgen Teich; Julien Lallet; Olivier Sentieys; Sébastien Pillement (ARCS, 2007)

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. - Jürgen Teich; Frank Hannig; Holger Ruckdeschel; Hritam Dutta; Dmitrij Kissler; Andrej Stravet (ERSA, 2007)

Massively Parallel Processor Architectures: A Co-design Approach. - Hritam Dutta; Frank Hannig; Alexey Kupriyanov; Dmitrij Kissler; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Bernard Pottier (ReCoSoC, 2007)

Efficient event-driven simulation of parallel processor architectures. - Alexey Kupriyanov; Dmitrij Kissler; Frank Hannig; Jürgen Teich (SCOPES, 2007)

Efficient control generation for mapping nested loop programs onto processor arrays. - Hritam Dutta; Frank Hannig; Holger Ruckdeschel; Jürgen Teich (J. Syst. Archit., 2007)

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. - Frank Hannig; Holger Ruckdeschel; Hritam Dutta; Jürgen Teich (ARC, 2008)

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. - Rainer Schaffer; Renate Merker; Frank Hannig; Jürgen Teich (DSD, 2008)

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. - Christophe Wolinski; Krzysztof Kuchcinski; Jürgen Teich; Frank Hannig (DSD, 2008)

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. - Christophe Wolinski; Krzysztof Kuchcinski; Jürgen Teich; Frank Hannig (FCCM, 2008)

Coarse-grained reconfiguration. - Sven Eisenhardt; Thomas Schweizer; Julio A. de Oliveira Filho; Tobias Oppold; Wolfgang Rosenstiel; Alexander Thomas; Jürgen Becker 001; Frank Hannig; Dmitrij Kissler; Hritam Dutta; Jürgen Teich; Heiko Hinkelmann; et al. (FPL, 2008)

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. - Christophe Wolinski; Krzysztof Kuchcinski; Jürgen Teich; Frank Hannig (FPL, 2008)

The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. - Frank Hannig; Holger Ruckdeschel; Jürgen Teich (MBMV, 2008)

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. - Hritam Dutta; Frank Hannig; Jürgen Teich (ARCS, 2009)

Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. - Frank Hannig; Hritam Dutta; Jürgen Teich (ARCS, 2009)

Impact of Loop Tiling on the Controller Logic of Acceleration Engines. - Hritam Dutta; Jiali Zhai; Frank Hannig; Jürgen Teich (ASAP, 2009)

Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. - Richard Membarth; Philipp Kutzer; Hritam Dutta; Frank Hannig; Jürgen Teich (ASAP, 2009)

Model-based synthesis and optimization of static multi-rate image processing algorithms. - Joachim Keinert; Hritam Dutta; Frank Hannig; Christian Haubelt; Jürgen Teich (DATE, 2009)

FPGA implementation of an invasive computing architecture. - Abdulazim Amouri; Farhadur Arifin; Frank Hannig; Jürgen Teich (FPT, 2009)

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. - Vahid Lari; Frank Hannig; Jürgen Teich (ICPP Workshops, 2009)

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. - Richard Membarth; Frank Hannig; Hritam Dutta; Jürgen Teich (SAMOS, 2009)

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. - Dmitrij Kissler; Andreas Strawetz; Frank Hannig; Jürgen Teich (J. Low Power Electron., 2009)

A holistic approach for tightly coupled reconfigurable parallel processors. - Hritam Dutta; Dmitrij Kissler; Frank Hannig; Alexey Kupriyanov; Jürgen Teich; Bernard Pottier (Microprocess. Microsystems, 2009)

Scheduling Techniques for High-Throughput Loop Accelerators. - Frank Hannig (2009)

Modeling and synthesis of communication subsystems for loop accelerator pipelines. - Hritam Dutta; Frank Hannig; Moritz Schmid; Joachim Keinert (ASAP, 2010)

Compilation techniques for CGRAs: exploring all parallelization approaches. - Tom Vander Aa; Praveen Raghavan; Scott A. Mahlke; Bjorn De Sutter; Aviral Shrivastava; Frank Hannig (CODES+ISSS, 2010)

A deeply pipelined and parallel architecture for denoising medical images. - Frank Hannig; Moritz Schmid; Jürgen Teich; Heinz Hornegger (FPT, 2010)

Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. - Richard Membarth; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (ARCS, 2011)

Decentralized dynamic resource management support for massively parallel processor arrays. - Vahid Lari; Andriy Narovlyanskyy; Frank Hannig; Jürgen Teich (ASAP, 2011)

Distributed Resource Reservation in Massively Parallel Processor Arrays. - Vahid Lari; Frank Hannig; Jürgen Teich (IPDPS Workshops, 2011)

Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. - Georgia Kouveli; Frank Hannig; Jan-Hugo Lupp; Jürgen Teich (MARC Symposium, 2011)

Detector defect correction of medical images on graphics processors. - Richard Membarth; Frank Hannig; Jürgen Teich; Gerhard Litz; Heinz Hornegger (Image Processing, 2011)

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. - Srinivas Boppu; Frank Hannig; Jürgen Teich; Roberto Perez-Andrade (ReConFig, 2011)

Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. - Richard Membarth; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (SASP, 2011)

Resource-aware programming and simulation of MPSoC architectures through extension of X10. - Frank Hannig; Sascha Roloff; Gregor Snelting; Jürgen Teich; Andreas Zwinkau (SCOPES, 2011)

Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. - Dmitrij Kissler; D. Gran; Zoran Salcic; Frank Hannig; Jürgen Teich (IEEE Embed. Syst. Lett., 2011)

Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. - Dmitrij Kissler; Frank Hannig; Jürgen Teich (J. Low Power Electron., 2011)

Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. - Richard Membarth; Jan-Hugo Lupp; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (ARCS, 2012)

Design of Low Power On-chip Processor Arrays. - Vahid Lari; Shravan Muddasani; Srinivas Boppu; Frank Hannig; Jürgen Teich (ASAP, 2012)

Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. - Sascha Roloff; Frank Hannig; Jürgen Teich (ASP-DAC, 2012)

A prototype of an invasive tightly-coupled processor array. - Shravan Muddasani; Srinivas Boppu; Frank Hannig; Boris Kuzmin; Vahid Lari; Jürgen Teich (DASIP, 2012)

Mastering Software Variant Explosion for GPU Accelerators. - Richard Membarth; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (Euro-Par Workshops, 2012)

Power Management Strategies for Serial RapidIO Endpoints in FPGAs. - Moritz Schmid; Frank Hannig; Jürgen Teich (FCCM, 2012)

An integrated simulation framework for invasive computing. - Michael Gerndt; Frank Hannig; Andreas Herkersdorf; Andreas Hollmann; Marcel Meyer; Sascha Roloff; Josef Weidendorfer; Thomas Wild; Aurang Zaib (FDL, 2012)

Generating Device-specific GPU Code for Local Operators in Medical Imaging. - Richard Membarth; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (IPDPS, 2012)

Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. - Richard Membarth; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (ISPDC, 2012)

Towards Domain-Specific Computing for Stencil Codes in HPC. - Richard Membarth; Frank Hannig; Jürgen Teich; Harald Köstler (SC Companion, 2012)

Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. - Sascha Roloff; Frank Hannig; Jürgen Teich (Map2MPSoC/SCOPES, 2012)

Hierarchical power management for adaptive tightly-coupled processor arrays. - Vahid Lari; Shravan Muddasani; Srinivas Boppu; Frank Hannig; Moritz Schmid; Jürgen Teich (ACM Trans. Design Autom. Electr. Syst., 2012)

Loop program mapping and compact code generation for programmable hardware accelerators. - Srinivas Boppu; Frank Hannig; Jürgen Teich (ASAP, 2013)

Symbolic parallelization of loop programs for massively parallel processor arrays. - Jürgen Teich; Alexandru Tanase; Frank Hannig (ASAP, 2013)

System integration of tightly-coupled processor arrays using reconfigurable buffer structures. - Frank Hannig; Moritz Schmid; Vahid Lari; Srinivas Boppu; Jürgen Teich (Conf. Computing Frontiers, 2013)

Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. - Éricles Rodrigues Sousa; Alexandru Tanase; Frank Hannig; Jürgen Teich (DASIP, 2013)

A prototype of an adaptive computer vision algorithm on MPSoC architecture. - Éricles Rodrigues Sousa; Alexandru Tanase; Frank Hannig; Jürgen Teich (DASIP, 2013)

High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. - Moritz Schmid; Frank Hannig; Alexandru Tanase; Jürgen Teich (PARCO, 2013)

Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. - Alexandru Tanase; Vahid Lari; Frank Hannig; Jürgen Teich (PARCO, 2013)

Real-timerange image preprocessing on FPGAs. - Moritz Schmid; Markus Blocherer; Frank Hannig; Jürgen Teich (ReConFig, 2013)

NoC simulation in heterogeneous architectures for PGAS programming model. - Sascha Roloff; Andreas Weichslgartner; Jan Heißwolf; Frank Hannig; Jürgen Teich (M-SCOPES, 2013)

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. - Deepak Gangadharan; Éricles Sousa; Vahid Lari; Frank Hannig; Jürgen Teich (ACSSC, 2014)

Towards Actor-oriented Programming on PGAS-based Multicore Architectures. - Sascha Roloff; Frank Hannig; Jürgen Teich (ARCS Workshops, 2014)

Domain-specific augmentations for High-Level Synthesis. - Moritz Schmid; Alexandru Tanase; Frank Hannig; Jürgen Teich; Vivek Singh Bhadouria; Dibyendu Ghoshal (ASAP, 2014)

Code generation from a domain-specific language for C-based HLS of hardware accelerators. - Oliver Reiche; Moritz Schmid; Frank Hannig; Richard Membarth; Jürgen Teich (CODES+ISSS, 2014)

Self-adaptive harris corner detector on heterogeneous many-core processor. - Johny Paul; Walter Stechele; Éricles Sousa; Vahid Lari; Frank Hannig; Jürgen Teich; Manfred Kröhnert; Tamim Asfour (DASIP, 2014)

Code generation for embedded heterogeneous architectures on android. - Richard Membarth; Oliver Reiche; Frank Hannig; Jürgen Teich (DATE, 2014)

Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. - Éricles Sousa; Deepak Gangadharan; Frank Hannig; Jürgen Teich (DSD, 2014)

ExaStencils: Advanced Stencil-Code Engineering. - Christian Lengauer; Sven Apel; Matthias Bolten; Armin Größlinger; Frank Hannig; Harald Köstler; Ulrich Rüde; Jürgen Teich; Alexander Grebhahn; Stefan Kronawitter; Sebastian Kuckuk; Hannah Rittich; et al. (Euro-Par Workshops (2), 2014)

An image processing library for C-based high-level synthesis. - Moritz Schmid; Nicolas Apelt; Frank Hannig; Jürgen Teich (FPL, 2014)

An Evaluation of Domain-Specific Language Technologies for Code Generation. - Christian Schmitt 003; Sebastian Kuckuk; Harald Köstler; Frank Hannig; Jürgen Teich (ICCSA (Workshops/Short Papers/Posters), 2014)

Symbolic inner loop parallelisation for massively parallel processor arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig (MEMOCODE, 2014)

ExaSlang: a domain-specific language for highly scalable multigrid solvers. - Christian Schmitt 003; Sebastian Kuckuk; Frank Hannig; Harald Köstler; Jürgen Teich (WOLFHPC@SC, 2014)

Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). - Frank Hannig; Dirk Koch; Daniel Ziener (CoRR, 2014)

Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). - Frank Hannig; Jürgen Teich (CoRR, 2014)

A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms. - Harald Köstler; Christian Schmitt 003; Sebastian Kuckuk; Frank Hannig; Jürgen Teich; Ulrich Rüde (CoRR, 2014)

Massively Parallel Processor Architectures for Resource-aware Computing. - Vahid Lari; Alexandru Tanase; Frank Hannig; Jürgen Teich (CoRR, 2014)

Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. - Moritz Schmid; Oliver Reiche; Christian Schmitt 003; Frank Hannig; Jürgen Teich (CoRR, 2014)

Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language. - Richard Membarth; Oliver Reiche; Christian Schmitt 003; Frank Hannig; Jürgen Teich; Markus Stürmer; Harald Köstler (J. Parallel Distributed Comput., 2014)

Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror. - Alexander Grebhahn; Sebastian Kuckuk; Christian Schmitt 003; Harald Köstler; Norbert Siegmund; Sven Apel; Frank Hannig; Jürgen Teich (Parallel Process. Lett., 2014)

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. - Frank Hannig; Vahid Lari; Srinivas Boppu; Alexandru Tanase; Oliver Reiche (ACM Trans. Embed. Comput. Syst., 2014)

Compact Code Generation for Tightly-Coupled Processor Arrays. - Srinivas Boppu; Frank Hannig; Jürgen Teich (J. Signal Process. Syst., 2014)

Symbolic Mapping of Loop Programs onto Processor Arrays. - Jürgen Teich; Alexandru Tanase; Frank Hannig (J. Signal Process. Syst., 2014)

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. - Vahid Lari; Alexandru Tanase; Jürgen Teich; Michael Witterauf; Faramarz Khosravi; Frank Hannig; Brett H. Meyer (AHS, 2015)

Loop coarsening in C-based High-Level Synthesis. - Moritz Schmid; Oliver Reiche; Frank Hannig; Jürgen Teich (ASAP, 2015)

On-demand fault-tolerant loop processing on massively parallel processor arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig; Vahid Lari (ASAP, 2015)

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. - Sascha Roloff; David Schafhauser; Frank Hannig; Jürgen Teich (DAC, 2015)

Invasive computing for predictable stream processing: a simulation-based case study. - Sascha Roloff; Stefan Wildermann; Frank Hannig; Jürgen Teich (ESTIMedia, 2015)

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. - Éricles Sousa; Frank Hannig; Jürgen Teich (IESS, 2015)

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig (MEMOCODE, 2015)

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. - Éricles Sousa; Frank Hannig; Jürgen Teich; Qingqing Chen 004; Ulf Schlichtmann (SCOPES, 2015)

Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). - Frank Hannig; Dietmar Fey; Anton Lokhmotov (CoRR, 2015)

Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). - Frank Hannig; Dirk Koch; Daniel Ziener (CoRR, 2015)

Automatic Optimization of Hardware Accelerators for Image Processing. - Oliver Reiche; Konrad Häublein; Marc Reichenbach; Frank Hannig; Jürgen Teich; Dietmar Fey (CoRR, 2015)

Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures. - Frank Hannig; Andreas Herkersdorf (J. Syst. Archit., 2015)

Resource-awareness on heterogeneous MPSoCs for image processing. - Johny Paul; Walter Stechele; Benjamin Oechslein; Christoph Erhardt; Jens Schedel; Daniel Lohmann; Wolfgang Schröder-Preikschat; Manfred Kröhnert; Tamim Asfour; Éricles Sousa; Vahid Lari; Frank Hannig; et al. (J. Syst. Archit., 2015)

Synthesis and optimization of image processing accelerators using domain knowledge. - Oliver Reiche; Konrad Häublein; Marc Reichenbach; Moritz Schmid; Frank Hannig; Jürgen Teich; Dietmar Fey (J. Syst. Archit., 2015)

A Quick Tour of High-Level Synthesis Solutions for FPGAs. - Frank Hannig (FPGAs for Software Programmers, 2016)

FPGA Versus Software Programming: Why, When, and How? - Dirk Koch; Daniel Ziener; Frank Hannig (FPGAs for Software Programmers, 2016)

HIPAcc. - Moritz Schmid; Oliver Reiche; Frank Hannig; Jürgen Teich (FPGAs for Software Programmers, 2016)

Big Data and HPC Acceleration with Vivado HLS. - Moritz Schmid; Christian Schmitt 003; Frank Hannig; Gorker Alp Malazgirt; Nehir Sönmez; Arda Yurdakul; Adrián Cristal (FPGAs for Software Programmers, 2016)

Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. - Michael Witterauf; Alexandru Tanase; Frank Hannig; Jürgen Teich (ASAP, 2016)

FPGA-based accelerator design from a domain-specific language. - M. Akif Ozkan; Oliver Reiche; Frank Hannig; Jürgen Teich (FPL, 2016)

Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. - Jörg Fickenscher; Oliver Reiche; Jens Schlumberger; Frank Hannig; Jürgen Teich (HLDVT, 2016)

ActorX10: an actor library for X10. - Sascha Roloff; Alexander Pöppl; Tobias Schwarzer; Stefan Wildermann; Michael Bader; Michael Glaß; Frank Hannig; Jürgen Teich (X10@PLDI, 2016)

Hybrid code description for developing fast and resource efficient image processing architectures. - Konrad Häublein; Marc Reichenbach; Oliver Reiche; M. Akif Ozkan; Dietmar Fey; Frank Hannig; Jürgen Teich (SAMOS, 2016)

Dark silicon management: an integrated and coordinated cross-layer approach. - Santiago Pagani; Lars Bauer; Qingqing Chen 004; Elisabeth Glocker; Frank Hannig; Andreas Herkersdorf; Heba Khdr; Anuj Pathania; Ulf Schlichtmann; Doris Schmitt-Landsiedel; Mark Sagi; Éricles Sousa; et al. (it Inf. Technol., 2016)

HIPAcc: A Domain-Specific Language and Compiler for Image Processing. - Richard Membarth; Oliver Reiche; Frank Hannig; Jürgen Teich; Mario Körner; Wieland Eckert (IEEE Trans. Parallel Distributed Syst., 2016)

Systems of Partial Differential Equations in ExaSlang. - Christian Schmitt 003; Sebastian Kuckuk; Frank Hannig; Jürgen Teich; Harald Köstler; Ulrich Rüde; Christian Lengauer (Software for Exascale Computing, 2016)

Efficiency in ILP processing by using orthogonality. - Marcel Brand; Frank Hannig; Alexandru Tanase; Jürgen Teich (ASAP, 2017)

Hardware design and analysis of efficient loop coarsening and border handling for image processing. - M. Akif Ozkan; Oliver Reiche; Frank Hannig; Jürgen Teich (ASAP, 2017)

High performance network-on-chip simulation by interval-based timing predictions. - Sascha Roloff; Frank Hannig; Jürgen Teich (ESTIMedia, 2017)

Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). - Oliver Reiche; M. Akif Ozkan; Richard Membarth; Jürgen Teich; Frank Hannig (ICCAD, 2017)

Convoy tracking for ADAS on embedded GPUs. - Jörg Fickenscher; Sebastian Reinhart; Frank Hannig; Jürgen Teich; Mohamed Essayed Bouzouraa (Intelligent Vehicles Symposium, 2017)

Auto-vectorization for image processing DSLs. - Oliver Reiche; Christof Kobylko; Frank Hannig; Jürgen Teich (LCTES, 2017)

Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. - Marcel Brand; Frank Hannig; Alexandru Tanase; Jürgen Teich (MCSoC, 2017)

TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. - Éricles Sousa; Arindam Chakraborty; Alexandru Tanase; Frank Hannig; Jürgen Teich (ReConFig, 2017)

A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. - Éricles Sousa; Alexandru Tanase; Frank Hannig; Jürgen Teich (ReConFig, 2017)

Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. - Michael Witterauf; Frank Hannig; Jürgen Teich (RSP, 2017)

A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. - Harald Köstler; Christian Schmitt 003; Sebastian Kuckuk; Stefan Kronawitter; Frank Hannig; Jürgen Teich; Ulrich Rüde; Christian Lengauer (Int. J. Comput. Sci. Eng., 2017)

Introduction to the special issue on architecture of computing systems. - Frank Hannig; João M. P. Cardoso; Dietmar Fey (J. Syst. Archit., 2017)

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. - Heba Khdr; Santiago Pagani; Éricles Sousa; Vahid Lari; Anuj Pathania; Frank Hannig; Muhammad Shafique 001; Jürgen Teich; Jörg Henkel (IEEE Trans. Computers, 2017)

Trends in Data Locality Abstractions for HPC Systems. - Didem Unat; Anshu Dubey; Torsten Hoefler; John Shalf; Mark James Abraham; Mauro Bianco; Bradford L. Chamberlain; Romain Cledat; H. Carter Edwards; Hal Finkel; Karl Fuerlinger; Frank Hannig; et al. (IEEE Trans. Parallel Distributed Syst., 2017)

A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. - Vivek Singh Bhadouria; Alexandru Tanase; Moritz Schmid; Frank Hannig; Jürgen Teich; Dibyendu Ghoshal (J. Signal Process. Syst., 2017)

Symbolic Parallelization of Nested Loop Programs - Alexandru-Petru Tanase; Frank Hannig; Jürgen Teich (Springer, 2018)

Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. - Ayesha Afzal; Christian Schmitt 003; Samer Alhaddad; Yevgen Grynko; Jürgen Teich; Jens Förstner; Frank Hannig (ASAP, 2018)

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. - Éricles Sousa; Michael Witterauf; Marcel Brand; Alexandru Tanase; Frank Hannig; Jürgen Teich (ASAP, 2018)

Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. - Jörg Fickenscher; Jens Schlumberger; Frank Hannig; Jürgen Teich; Mohamed Essayed Bouzouraa (DATE, 2018)

OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. - Tobias Kenter; Gopinath Mahale; Samer Alhaddad; Yevgen Grynko; Christian Schmitt 003; Ayesha Afzal; Frank Hannig; Jens Förstner; Christian Plessl (FCCM, 2018)

Automatic Kernel Fusion for Image Processing DSLs. - Bo Qiao 004; Oliver Reiche; Frank Hannig; Jürgen Teich (SCOPES, 2018)

Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. - Jörg Fickenscher; Frank Hannig; Jürgen Teich; Mohamed Essayed Bouzouraa (VEHITS, 2018)

Special issue on heterogeneous real-time image processing. - Dietmar Fey; Frank Hannig (J. Real Time Image Process., 2018)

Automating the Development of High-Performance Multigrid Solvers. - Christian Schmitt 003; Stefan Kronawitter; Frank Hannig; Jürgen Teich; Christian Lengauer (Proc. IEEE, 2018)

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. - Christian Schmitt 003; Moritz Schmid; Sebastian Kuckuk; Harald Köstler; Jürgen Teich; Frank Hannig (Parallel Process. Lett., 2018)

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig (ACM Trans. Embed. Comput. Syst., 2018)

Loop Parallelization Techniques for FPGA Accelerator Synthesis. - Oliver Reiche; M. Akif Ozkan; Frank Hannig; Jürgen Teich; Moritz Schmid (J. Signal Process. Syst., 2018)

Modeling and Simulation of Invasive Applications and Architectures. - Sascha Roloff; Frank Hannig; Jürgen Teich (Springer, 2019)

DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. - Jörg Fickenscher; Frank Hannig; Jürgen Teich (ARCS, 2019)

Anytime instructions for programmable accuracy floating-point arithmetic. - Marcel Brand; Michael Witterauf; Frank Hannig; Jürgen Teich (CF, 2019)

From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. - Bo Qiao 004; Oliver Reiche; Frank Hannig; Jürgen Teich (CGO, 2019)

Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. - Michael Witterauf; Frank Hannig; Jürgen Teich (MEMOCODE, 2019)

SYCL Code Generation for Multigrid Methods. - Stefan Groth; Christian Schmitt 003; Jürgen Teich; Frank Hannig (SCOPES, 2019)

Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. - Christian Heidorn; Michael Witterauf; Frank Hannig; Jürgen Teich (J. Comput., 2019)

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. - Richard Membarth; Hritam Dutta; Frank Hannig; Jürgen Teich (Trans. High Perform. Embed. Archit. Compil., 2019)

From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. - Bo Qiao 004; Oliver Reiche; Frank Hannig; Jürgen Teich (Zenodo, 2019)

From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. - Bo Qiao 004; Oliver Reiche; Frank Hannig; Jürgen Teich (Zenodo, 2019)

Message from the Conference Chairs - ASAP 2020. - Dirk Koch; Frank Hannig; Javier Navaridas (ASAP, 2020)

A runtime system for finite element methods in a partitioned global address space. - Stefan Groth; Daniel Grünewald; Jürgen Teich; Frank Hannig (CF, 2020)

The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. - Bo Qiao 004; M. Akif Özkan; Jürgen Teich; Frank Hannig (DAC, 2020)

HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. - Samer Alhaddad; Jens Förstner; Stefan Groth; Daniel Grünewald; Yevgen Grynko; Frank Hannig; Tobias Kenter; Franz-Josef Pfreundt; Christian Plessl; Merlind Schotte; Thomas Steinke 001; Jürgen Teich; et al. (Euro-Par Workshops, 2020)

Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. - Bo Qiao 004; Oliver Reiche; Jürgen Teich; Frank Hannig (GPGPU@PPoPP, 2020)

Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. - Christian Heidorn; Frank Hannig; Jürgen Teich (SCOPES, 2020)

Efficient parallel reduction on GPUs with Hipacc. - Bo Qiao 004; Oliver Reiche; M. Akif Özkan; Jürgen Teich; Frank Hannig (SCOPES, 2020)

Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. - Arvind Thumatti K. R.; Marcel Brand; Christian Heidorn; Srinivas Boppu; Frank Hannig; Jürgen Teich (VDAT, 2020)

A bibliometric approach for detecting the gender gap in computer science. - Sandra Mattauch; Katja Lohmann; Frank Hannig; Daniel Lohmann; Jürgen Teich (Commun. ACM, 2020)

Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. - Muhammad Sabih; Frank Hannig; Jürgen Teich (CoRR, 2020)

AnyHLS: High-Level Synthesis With Partial Evaluation. - M. Akif Özkan; Arsène Pérard-Gayot; Richard Membarth; Philipp Slusallek; Roland Leißa; Sebastian Hack; Jürgen Teich; Frank Hannig (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

ExaStencils: Advanced Multigrid Solver Generation. - Christian Lengauer; Sven Apel; Matthias Bolten; Shigeru Chiba; Ulrich Rüde; Jürgen Teich; Armin Größlinger; Frank Hannig; Harald Köstler; Lisa Claus; Alexander Grebhahn; Stefan Groth; et al. (Software for Exascale Computing, 2020)

Fault-Tolerant Low-Precision DNNs using Explainable AI. - Muhammad Sabih; Frank Hannig; Jürgen Teich (DSN Workshops, 2021)

A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. - Patrick Plagwitz; Frank Hannig; Martin Ströbel; Christoph Strohmeyer; Jürgen Teich (FCCM, 2021)

Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. - Christian Heidorn; Dominik Walter; Yunus Emre Candir; Frank Hannig; Jürgen Teich (FPL, 2021)

An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. - Bo Qiao 004; Jürgen Teich; Frank Hannig (IPDPS Workshops, 2021)

Efficient Application of Tensor Core Units for Convolving Images. - Stefan Groth; Jürgen Teich; Frank Hannig (SCOPES, 2021)

Open Source Hardware. - Frank Hannig; Jürgen Teich (Computer, 2021)

*-Predictable MPSoC execution of real-time control applications using invasive computing. - Marcel Brand; Michael Witterauf; Éricles Sousa; Alexandru Tanase; Frank Hannig; Jürgen Teich (Concurr. Comput. Pract. Exp., 2021)

Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). - Frank Hannig; Paolo Meloni; Matteo Spallanzani; Matthias Ziegler 001 (CoRR, 2021)

HipaccVX: wedding of OpenVX and DSL-based code generation. - M. Akif Özkan; Burak Ok; Bo Qiao 004; Jürgen Teich; Frank Hannig (J. Real Time Image Process., 2021)

Symbolic Loop Compilation for Tightly Coupled Processor Arrays. - Michael Witterauf; Dominik Walter; Frank Hannig; Jürgen Teich (ACM Trans. Embed. Comput. Syst., 2021)

Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. - Frank Hannig; Dirk Koch (J. Signal Process. Syst., 2021)

DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. - Muhammad Sabih; Frank Hannig; Jürgen Teich (EuroMLSys@EuroSys, 2022)

TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. - Patrick Plagwitz; Frank Hannig; Jürgen Teich (FPL, 2022)

MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. - Muhammad Sabih; Ashutosh Mishra; Frank Hannig; Jürgen Teich (IGSC, 2022)

Hardware-Aware Evolutionary Filter Pruning. - Christian Heidorn; Nicolai Meyerhöfer; Christian Schinabeck; Frank Hannig; Jürgen Teich (SAMOS, 2022)

The HighPerMeshes framework for numerical algorithms on unstructured grids. - Samer Alhaddad; Jens Förstner; Stefan Groth; Daniel Grünewald; Yevgen Grynko; Frank Hannig; Tobias Kenter; Franz-Josef Pfreundt; Christian Plessl; Merlind Schotte; Thomas Steinke 001; Jürgen Teich; et al. (Concurr. Comput. Pract. Exp., 2022)

Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. - Marcel Brand; Frank Hannig; Oliver Keszöcze; Jürgen Teich (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Special Issue on Applied Reconfigurable Computing. - Frank Hannig; Steven Derrien (J. Signal Process. Syst., 2022)

Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. - Muhammad Sabih; Mikail Yayla; Frank Hannig; Jürgen Teich; Jian-Jia Chen (EuroMLSys@EuroSys, 2023)

To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. - Patrick Plagwitz; Frank Hannig; Jürgen Teich; Oliver Keszöcze (CoRR, 2023)

SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. - Patrick Plagwitz; Frank Hannig; Jürgen Teich; Oliver Keszöcze (ARC, 2024)

Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. - Dominik Walter; Thomas Adamtschuk; Frank Hannig; Jürgen Teich (ASAP, 2024)

Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. - Muhammad Sabih; Batuhan Sesli; Frank Hannig; Jürgen Teich (DATE, 2024)

DSL-Based SNN Accelerator Design Using Chisel. - Patrick Plagwitz; Frank Hannig; Jürgen Teich; Oliver Keszöcze (DSD, 2024)

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. - Muhammad Sabih; Abrarul Karim; Jakob Wittmann; Frank Hannig; Jürgen Teich (ICFPT, 2024)

ALPACA: An Accelerator Chip for Nested Loop Programs. - Dominik Walter; Marcel Brand; Christian Heidorn; Michael Witterauf; Frank Hannig; Jürgen Teich (ISCAS, 2024)

Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. - Christian Heidorn; Frank Hannig; Dominik Riedelbauch; Christoph Strohmeyer; Jürgen Teich (VEHITS, 2024)

OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. - Christian Heidorn; Frank Hannig; Dominik Riedelbauch; Christoph Strohmeyer; Jürgen Teich (CoRR, 2024)

Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. - Christian Heidorn; Muhammad Sabih; Nicolai Meyerhöfer; Christian Schinabeck; Jürgen Teich; Frank Hannig (Int. J. Parallel Program., 2024)

Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs. - Dominik Walter; Marita Halm; Daniel Seidel; Indrayudh Ghosh; Christian Heidorn; Frank Hannig; Jürgen Teich (CoRR, 2025)

Evaluation of CGRA Toolchains. - Dominik Walter; Marita Halm; Daniel Seidel; Indrayudh Ghosh; Christian Heidorn; Frank Hannig; Jürgen Teich (CoRR, 2025)

On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. - Mark Deutel; Frank Hannig; Christopher Mutschler; Jürgen Teich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)