Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ISCAS (1), 1999)

A compact modular architecture for high-speed binary sorting. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ICASSP, 2000)

Higher radix Kogge-Stone parallel prefix adder architectures. - Frank K. Gürkaynak; Yusuf Leblebici; Laurent Chaouat; Patrik J. McGuinness (ISCAS, 2000)

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ISCAS, 2000)

A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (VLSI Design, 2000)

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. - Thomas Villiger; Stephan Oetiker; Frank K. Gürkaynak; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (ASYNC, 2002)

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. - Adrian K. Lutz; Jürg Treichler; Frank K. Gürkaynak; Hubert Kaeslin; Gérard Basler; Antonia Erni; Stephan Reichmuth; Pieter Rommens; Stephan Oetiker; Wolfgang Fichtner (CHES, 2002)

Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. - Thomas Villiger; Hubert Kaeslin; Frank K. Gürkaynak; Stephan Oetiker; Wolfgang Fichtner (ASYNC, 2003)

Variable delay ripple carry adder with carry chain interrupt detection. - Andreas Burg 001; Frank K. Gürkaynak; Hubert Kaeslin; Wolfgang Fichtner (ISCAS (5), 2003)

Towards an AES crypto-chip resistant to differential power analysis. - Norbert Pramstaller; Frank K. Gürkaynak; Simon Haene; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ESSCIRC, 2004)

A 2 Gb/s balanced AES crypto-chip implementation. - Frank K. Gürkaynak; Andreas Burg 001; Norbert Felber; Wolfgang Fichtner; D. Gasser; Franco Hug; Hubert Kaeslin (ACM Great Lakes Symposium on VLSI, 2004)

Power-Analysis Attack on an ASIC AES implementation. - Siddika Berna Örs; Frank K. Gürkaynak; Elisabeth Oswald; Bart Preneel (ITCC (2), 2004)

Improving DPA security by using globally-asynchronous locally-synchronous systems. - Frank K. Gürkaynak; Stephan Oetiker; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ESSCIRC, 2005)

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. - Frank K. Gürkaynak; Stephan Oetiker; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (FMGALS@MEMOCODE, 2005)

GALS at ETH Zurich: Success or Failure. - Frank K. Gürkaynak; Stephan Oetiker; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ASYNC, 2006)

GALS system design: side channel attack secure cryptographic accelerators. - Frank Kagan Gürkaynak (2006)

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. - Milos Stanisavljevic; Frank K. Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani (ACM Great Lakes Symposium on VLSI, 2007)

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. - Milos Stanisavljevic; Frank Kagan Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani (Nano-Net, 2007)

Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. - Milos Krstic; Eckhard Grass; Frank K. Gürkaynak; Pascal Vivet (IEEE Des. Test Comput., 2007)

Design space exploration for field programmable compressor trees. - Seyed-Hosein Attarzadeh-Niaki; Alessandro Cevrero; Philip Brisk; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (CASES, 2008)

A Generic Standard Cell Design Methodology for Differential Circuit Styles. - Stéphane Badel; Erdem Guleyupoglu; Ozgur Inac; Anna Pena Martinez; Paolo Vietti; Frank K. Gürkaynak; Yusuf Leblebici (DATE, 2008)

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. - Carlotta Guiducci; Alexandre Schmid; Frank K. Gürkaynak; Yusuf Leblebici (DATE, 2008)

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (FPGA, 2008)

Improving the power-delay product in SCL circuits using source follower output stage. - Armin Tajalli; Frank K. Gürkaynak; Yusuf Leblebici; Massimo Alioto; Elizabeth J. Brauer (ISCAS, 2008)

GALS for Bursty Data Transfer based on Clock Coupling. - Milos Krstic; Xin Fan 003; Eckhard Grass; Frank K. Gürkaynak (FMGALS@DATE, 2009)

The Certicom Challenges ECC2-X. - Daniel V. Bailey; Brian Baldwin; Lejla Batina; Daniel J. Bernstein; Peter Birkner; Joppe W. Bos; Gauthier Van Damme; Giacomo de Meulenaer; Junfeng Fan; Tim Güneysu; Frank K. Gürkaynak; Thorsten Kleinjung; et al. (IACR Cryptol. ePrint Arch., 2009)

Breaking ECC2K-130. - Daniel V. Bailey; Lejla Batina; Daniel J. Bernstein; Peter Birkner; Joppe W. Bos; Hsieh-Chung Chen; Chen-Mou Cheng; Gauthier Van Damme; Giacomo de Meulenaer; Luis J. Dominguez Perez; Junfeng Fan; Tim Güneysu; et al. (IACR Cryptol. ePrint Arch., 2009)

A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. - Omer Can Akgun; Frank K. Gürkaynak; Yusuf Leblebici (Int. J. Circuit Theory Appl., 2009)

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. - Francesco Regazzoni 001; Thomas Eisenbarth 001; Axel Poschmann; Johann Großschädl; Frank K. Gürkaynak; Marco Macchetti; Zeynep Toprak Deniz; Laura Pozzi 001; Christof Paar; Yusuf Leblebici; Paolo Ienne (Trans. Comput. Sci., 2009)

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Seyed-Hosein Attarzadeh-Niaki; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

Developing a Hardware Evaluation Method for SHA-3 Candidates. - Luca Henzen; Pietro Gendotti; Patrice Guillet; Enrico Pargaetzi; Martin Zoller; Frank K. Gürkaynak (CHES, 2010)

Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields. - Deniz Karakoyunlu; Frank Kagan Gürkaynak; Berk Sunar; Yusuf Leblebici (IET Inf. Secur., 2010)

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. - Jeremy Constantin; Andreas Burg 001; Frank K. Gürkaynak (ASAP, 2012)

A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. - Pierre Greisen; Richard Emler; Michael Schaffner; Simon Heinzle; Frank K. Gürkaynak (VLSI-SoC, 2012)

Spatially-Varying Image Warping: Evaluations and VLSI Implementations. - Pierre Greisen; Michael Schaffner; Danny Luu; Val Mikos; Simon Heinzle; Frank K. Gürkaynak; Aljoscha Smolic (VLSI-SoC (Selected Papers), 2012)

FPGA-Based High-Speed Authenticated Encryption System. - Michael Muehlberghuber; Christoph Keller; Frank K. Gürkaynak; Norbert Felber (VLSI-SoC (Selected Papers), 2012)

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. - Jeremy Constantin; Andreas Burg 001; Frank K. Gürkaynak (IACR Cryptol. ePrint Arch., 2012)

MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. - Michael Schaffner; Pierre Greisen; Simon Heinzle; Frank K. Gürkaynak; Hubert Kaeslin; Aljoscha Smolic (ESSCIRC, 2013)

Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. - Michael Muehlberghuber; Frank K. Gürkaynak; Thomas Korak; Philipp Dunst; Michael Hutter (HASP@ISCA, 2013)

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. - Michael Schaffner; Pascal A. Hager; Lukas Cavigelli; Z. Fang; Pierre Greisen; Frank K. Gürkaynak; Aljoscha Smolic; Hubert Kaeslin; Luca Benini (VLSI-SoC (Selected Papers), 2013)

A real-time 720p feature extraction core based on Semantic Kernels Binarized. - Michael Schaffner; Pascal Hager; Lukas Cavigelli; Pierre Greisen; Frank K. Gürkaynak; Hubert Kaeslin (VLSI-SoC, 2013)

An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. - Michael Schaffner; Frank K. Gürkaynak; Aljoscha Smolic; Hubert Kaeslin; Luca Benini (DAC, 2014)

Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. - Christoph Keller; Frank K. Gürkaynak; Hubert Kaeslin; Norbert Felber (ISCAS, 2014)

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. - Michael Schaffner; Frank K. Gürkaynak; Aljoscha Smolic; Luca Benini (DATE, 2015)

Automatic multiview synthesis - Towards a mobile system on a chip. - Michael Schaffner; Frank K. Gürkaynak; Hubert Kaeslin; Luca Benini; Aljosa Smolic (VCIP, 2015)

Automatic multiview synthesis - Prototype demo. - Michael Schaffner; Frank K. Gürkaynak; Hubert Kaeslin; Luca Benini; Aljosa Smolic (VCIP, 2015)

Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters. - Michael Schaffner; Michael Gautschi; Frank K. Gürkaynak; Luca Benini (ARITH, 2016)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

High-efficiency logarithmic number unit design based on an improved cotransformation scheme. - Youri Popoff; Florian Scheidegger; Michael Schaffner; Michael Gautschi; Frank K. Gürkaynak; Luca Benini (DATE, 2016)

Approximate 32-bit floating-point unit design with 53% power-area product reduction. - Vincent Camus; Jeremy Schlachter; Christian C. Enz; Michael Gautschi; Frank K. Gürkaynak (ESSCIRC, 2016)

4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. - Michael Gautschi; Michael Schaffner; Frank K. Gürkaynak; Luca Benini (ISSCC, 2016)

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. - Michael Schaffner; Frank K. Gürkaynak; Pierre Greisen; Hubert Kaeslin; Luca Benini; Aljosa Smolic (IEEE Trans. Circuits Syst. Video Technol., 2016)

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. - Frank K. Gürkaynak; Robert Schilling; Michael Muehlberghuber; Francesco Conti 001; Stefan Mangard; Luca Benini (CS2@HiPEAC, 2017)

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm. - Florian Glaser; Stefan Mach; Abbas Rahimi; Frank K. Gürkaynak; Qiuting Huang; Luca Benini (CoRR, 2017)

Leakage Bounds for Gaussian Side Channels. - Thomas Unterluggauer; Thomas Korak; Stefan Mangard; Robert Schilling; Luca Benini; Frank K. Gürkaynak; Michael Muehlberghuber (IACR Cryptol. ePrint Arch., 2017)

An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster. - Michael Gautschi; Michael Schaffner; Frank K. Gürkaynak; Luca Benini (IEEE J. Solid State Circuits, 2017)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. - Francesco Conti 001; Robert Schilling; Pasquale Davide Schiavone; Antonio Pullini; Davide Rossi; Frank Kagan Gürkaynak; Michael Muehlberghuber; Michael Gautschi; Igor Loi; Germain Haugou; Stefan Mangard; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. - Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High speed ASIC implementations of leakage-resilient cryptography. - Robert Schilling; Thomas Unterluggauer; Stefan Mangard; Frank K. Gürkaynak; Michael Muehlberghuber; Luca Benini (DATE, 2018)

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. - Florian Glaser; Stefan Mach; Abbas Rahimi; Frank K. Gürkaynak; Qiuting Huang; Luca Benini (ISCAS, 2018)

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. - Fabian Schuiki; Michael Schaffner; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Computers, 2019)

XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs. - Dionysios Diamantopoulos; Florian Scheidegger; Stefan Mach; Fabian Schuiki; Germain Haugou; Michael Schaffner; Frank K. Gürkaynak; Christoph Hagleitner; A. Cristiano I. Malossi; Luca Benini (COOL CHIPS, 2020)

The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform. - Aizea Lojo; Leire Rubio; Jesus Miguel Ruano; Tania Di Mascio; Luigi Pomante; Enrico Ferrari; Ignacio Garcìa Vega; Frank K. Gürkaynak; Mikel Labayen Esnaola; Vanessa Orani; Jaume Abella 001 (DSD, 2020)

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. - Nils Wistoff; Moritz Schneider 001; Frank K. Gürkaynak; Luca Benini; Gernot Heiser (CoRR, 2020)

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. - Nils Wistoff; Moritz Schneider 001; Frank K. Gürkaynak; Luca Benini; Gernot Heiser (DATE, 2021)

A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. - Thomas Benz; Luca Bertaccini; Florian Zaruba; Fabian Schuiki; Frank K. Gürkaynak; Luca Benini (ESSCIRC, 2021)

Security, Reliability and Test Aspects of the RISC-V Ecosystem. - Jaume Abella 001; Sergi Alcaide; Jens Anders; Francisco Bas; Steffen Becker 001; Elke De Mulder; Nourhan Elhamawy; Frank K. Gürkaynak; Helena Handschuh; Carles Hernández 001; Michael Hutter; Leonidas Kosmidis; et al. (ETS, 2021)

Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. - Pasquale Davide Schiavone; Davide Rossi; Alfio Di Mauro; Frank K. Gürkaynak; Timothy Saxe; Mao Wang; Ket Chong Yap; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. - Gianna Paulin; Matheus A. Cavalcante; Paul Scheffler; Luca Bertaccini; Yichao Zhang 003; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. - Michael Rogenmoser; Nils Wistoff; Pirmin Vogel; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

CONVOLVE: Smart and seamless design of smart edge processors. - Manil Dev Gomony; Floran de Putter; Anteneh Gebregiorgis; Gianna Paulin; Linyan Mei; Vikram Jain; Said Hamdioui; Victor Sanchez; Tobias Grosser; Marc Geilen; Marian Verhelst; Frank K. Zenke; et al. (CoRR, 2022)

PetaOps/W edge-AI $ mu$ Processors: Myth or reality? - Manil Dev Gomony; Floran de Putter; Anteneh Gebregiorgis; Gianna Paulin; Linyan Mei; Vikram Jain; Said Hamdioui; Victor Sanchez; Tobias Grosser; Marc Geilen; Marian Verhelst; Friedemann Zenke; et al. (DATE, 2023)

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. - MohammadHossein AskariHemmat; Théo Dupuis; Yoan Fournier; Nizar El Zarif; Matheus A. Cavalcante; Matteo Perotti; Frank K. Gürkaynak; Luca Benini; François Leduc-Primeau; Yvon Savaria; Jean-Pierre David (ISCAS, 2023)

FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. - Tim Fischer 001; Michael Rogenmoser; Matheus A. Cavalcante; Frank K. Gürkaynak; Luca Benini (CoRR, 2023)

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. - Nils Wistoff; Moritz Schneider 001; Frank K. Gürkaynak; Gernot Heiser; Luca Benini (IEEE Trans. Computers, 2023)

FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. - Tim Fischer 001; Michael Rogenmoser; Matheus A. Cavalcante; Frank K. Gürkaynak; Luca Benini (IEEE Des. Test, 2023)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC. - Philippe Sauter; Thomas Benz; Paul Scheffler; Zerun Jiang; Beat Muheim; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? - Philippe Sauter; Thomas Benz; Paul Scheffler; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS. - Paul Scheffler; Philippe Sauter; Thomas Benz; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC. - Michael Rogenmoser; Philip Wiese; Bruno E. Forlin; Frank K. Gürkaynak; Paolo Rech; Alessandra Menicucci; Marco Ottavi; Luca Benini (CoRR, 2024)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support. - Tim Fischer 001; Michael Rogenmoser; Thomas Benz; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon. - Philippe Sauter; Thomas Benz; Paul Scheffler; Hannah Pochert; Luisa Wüthrich; Martin Poviser; Beat Muheim; Frank K. Gürkaynak; Luca Benini (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips. - Cyril Koenig; Enrico Zelioli; Frank K. Gürkaynak; Luca Benini (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support. - Tim Fischer 001; Michael Rogenmoser; Thomas Benz; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS. - Philippe Sauter; Thomas Benz; Paul Scheffler; Martin Poviser; Frank K. Gürkaynak; Luca Benini (CoRR, 2025)