DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. - Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee 004; Erik Jan Marinissen (ITC, 2012)

3DIC from concept to reality. - Frank Lee 004; Bill Shen; Willy Chen; Suk Lee (ASP-DAC, 2013)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs. - Sandeep Kumar Goel; Min-Jer Wang; Saman Adham; Ashok Mehta; Frank Lee 004 (VLSI-DAT, 2014)

Efficient observation-point insertion for diagnosability enhancement in digital circuits. - Zipeng Li; Sandeep Kumar Goel; Frank Lee 004; Krishnendu Chakrabarty (ITC, 2015)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling. - Shenggao Li; Chien-Chun Tsai; Eric Soenen; Frank J. C. Lee; Cheng-Hsiang Hsieh (A-SSCC, 2021)

Physical Design for 3D Chiplets and System Integration. - Frank J. C. Lee (ISPD, 2021)

Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. - Sandeep Kumar Goel; Ankita Patidar; Frank Lee 004 (ETS, 2024)

Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. - Sandeep Kumar Goel; Moiz Khan; Ankita Patidar; Frank Lee 004; Vuong Nguyen; Bharath Shankaranarayanan; Doo Kim; Manish Arora (ITC, 2024)

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. - Sandeep Kumar Goel; Ankita Patidar; Moiz Khan; Frank Lee 004; Anshuman Chandra; Martin Keim; Naim Lemar; Jonathan Gaudet; Quoc Phan; Vidya Neerkundar (ITC, 2024)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology. - Tsung-Che Lu; Chin-Ming Fu; Wei-Hsiang Wang; Fred Kuo; Chih-Hsien Chang; Kenny Hsieh; King-Ho Tam; Tze-Chiang Huang; Tom Chen 002; Mei Wong; Wei-pin Changchien; Frank Lee 004 (VLSI Technology and Circuits, 2024)

TSMC in the Silicon Photonics Era - an Electrical Perspective. - Mikael Sahrling; Shenggao Li; Frank Lee 004; Stefan Rusu (OFC, 2025)