# Frank Liu

According to our database

Collaborative distances:

^{1}, Frank Liu authored at least 62 papers between 2002 and 2017.Collaborative distances:

## Awards

## IEEE Fellow

IEEE Fellow 2017, "For contributions to design for manufacturability of VLSI circuits".

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2017

Beautiful and Damned. Combined Effect of Content Quality and Social Ties on User Engagement.

IEEE Trans. Knowl. Data Eng., 2017

Highlights of ICCAD 2016.

IEEE Design & Test, 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.

Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale.

Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

2016

From the Heart of Silicon Valley to the Hill Country - Highlights of ICCAD 2015.

IEEE Design & Test, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.

Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015

Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Efficiently Constructing Mosaics from Video Collections.

Proceedings of the 2015 IEEE Winter Conference on Applications of Computer Vision, 2015

STAC-A2™ benchmark on POWER8.

Proceedings of the 8th Workshop on High Performance Computational Finance, 2015

2014

Rivers and Electric Networks: Crossing Disciplines in Modeling and Simulation.

Foundations and Trends in Electronic Design Automation, 2014

Applying microprocessor analysis methods to river network modelling.

Environmental Modelling and Software, 2014

IFM: A Scalable High Resolution Flood Modeling Framework.

Proceedings of the Euro-Par 2014 Parallel Processing, 2014

A Time-Unrolling Method to Compute Sensitivity of Dynamic Systems.

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-speed real-time multi-channel data-acquisition unit: Challenges and results.

Proceedings of the 11th IEEE Consumer Communications and Networking Conference, 2014

2013

A 0.026mm

^{2}5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

Spatial variation decomposition via sparse regression.

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2012 TAU power grid simulation contest: Benchmark suite and results.

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Dynamic river network simulation at large scale.

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Pure nodal analysis for efficient on-chip interconnect model order reduction.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2011 TAU power grid simulation contest: Benchmark suite and results.

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.

IEEE Trans. VLSI Syst., 2010

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.

IEEE Trans. VLSI Syst., 2010

Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design.

IEEE Design & Test of Computers, 2010

Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation.

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Physical design techniques for optimizing RTA-induced variations.

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation.

IEEE Trans. VLSI Syst., 2009

Modeling of layout-dependent stress effect in CMOS design.

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Variability analysis under layout pattern-dependent rapid-thermal annealing process.

Proceedings of the 46th Design Automation Conference, 2009

Predicting variability in nanoscale lithography processes.

Proceedings of the 46th Design Automation Conference, 2009

2008

Metrics Used in Physical Design.

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis.

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Root-Finding Method for Assessing SRAM Stability.

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.

Proceedings of the 45th Design Automation Conference, 2008

2007

Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.

IEEE Trans. VLSI Syst., 2007

Integrated Placement and Skew Optimization for Rotary Clocking.

IEEE Trans. VLSI Syst., 2007

A computer vision method to locate cold spots in foods in microwave sterilization processes.

Pattern Recognition, 2007

An efficient method for statistical circuit simulation.

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Efficient computation of current flow in signal wires for reliability analysis.

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Fast statistical circuit analysis with finite-point based transistor model.

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

The Impact of NBTI on the Performance of Combinational and Sequential Circuits.

Proceedings of the 44th Design Automation Conference, 2007

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.

Proceedings of the 44th Design Automation Conference, 2007

A General Framework for Spatial Correlation Modeling in VLSI Design.

Proceedings of the 44th Design Automation Conference, 2007

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Practical variation-aware interconnect delay and slew analysis for statistical timing verification.

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Integrated placement and skew optimization for rotary clocking.

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A practical method to estimate interconnect responses to variabilities.

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Circuit Optimization Using Scale Based Sensitivities.

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.

Proceedings of the 2005 Design, 2005

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.

Proceedings of the 42nd Design Automation Conference, 2005

2004

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Closed-form delay and slew metrics made easy.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals.

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Variational delay metrics for interconnect timing analysis.

Proceedings of the 41th Design Automation Conference, 2004

2003

Closed form expressions for extending step delay and slew metrics to ramp inputs.

Proceedings of the 2003 International Symposium on Physical Design, 2003

Full chip leakage estimation considering power supply and temperature variations.

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Delay and slew metrics using the lognormal distribution.

Proceedings of the 40th Design Automation Conference, 2003

2002

PERI: a technique for extending delay and slew metrics to ramp inputs.

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Test structures for delay variability.

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

A delay metric for RC circuits based on the Weibull distribution.

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002