A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. - Jan Mulder; Christopher M. Ward; Chi-Hung Lin; David Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; Rudy J. van de Plassche; Klaas Bult; Frank M. L. van der Goes (IEEE J. Solid State Circuits, 2004)

A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. - Chi-Hung Lin; Frank M. L. van der Goes; Jan R. Westra; Jan Mulder; Yu Lin; Erol Arslan; Emre Ayranci; Xiaodong Liu; Klaas Bult (ISSCC, 2009)

A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. - Chi-Hung Lin; Frank M. L. van der Goes; Jan R. Westra; Jan Mulder; Yu Lin; Erol Arslan; Emre Ayranci; Xiaodong Liu; Klaas Bult (IEEE J. Solid State Circuits, 2009)

An 800MS/s dual-residue pipeline ADC in 40nm CMOS. - Jan Mulder; Frank M. L. van der Goes; Davide Vecchi; Jan R. Westra; Emre Ayranci; Christopher M. Ward; Jiansong Wan; Klaas Bult (ISSCC, 2011)

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. - Davide Vecchi; Jan Mulder; Frank M. L. van der Goes; Jan R. Westra; Emre Ayranci; Christopher M. Ward; Jiansong Wan; Klaas Bult (IEEE J. Solid State Circuits, 2011)

A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS. - Silvian Spiridon; Johan van der Tang; Han Yan; Hua-feng Chen; Davide Guermandi; Xiaodong Liu; Erol Arslan; Frank M. L. van der Goes; Klaas Bult (IEEE J. Solid State Circuits, 2013)

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. - Jan R. Westra; Jan Mulder; Yi Ke; Davide Vecchi; Xiaodong Liu; Erol Arslan; Jiansong Wan; Qiongna Zhang; Sijia Wang; Frank M. L. van der Goes; Klaas Bult (CICC, 2014)

A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (ESSCIRC, 2014)

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. - Frank M. L. van der Goes; Christopher M. Ward; Santosh Astgimath; Han Yan; Jeff Riley; Jan Mulder; Sijia Wang; Klaas Bult (ISSCC, 2014)

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. - Jan R. Westra; Jan Mulder; Yi Ke; Davide Vecchi; Xiaodong Liu; Erol Arslan; Jiansong Wan; Qiongna Zhang; Sijia Wang; Frank M. L. van der Goes; Klaas Bult (ISSCC, 2014)

A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. - Frank M. L. van der Goes; Christopher M. Ward; Santosh Astgimath; Han Yan; Jeff Riley; Zeng Zeng; Jan Mulder; Sijia Wang; Klaas Bult (IEEE J. Solid State Circuits, 2014)

A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. - Md Shakil Akter; Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (ESSCIRC, 2015)

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (IEEE J. Solid State Circuits, 2015)

A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (ESSCIRC, 2017)

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier. - Md Shakil Akter; Rohan Sehgal; Frank M. L. van der Goes; Kofi A. A. Makinwa; Klaas Bult (IEEE J. Solid State Circuits, 2018)

A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (IEEE J. Solid State Circuits, 2018)