Design of a 10GHz clock distribution network using coupled standing-wave oscillators. - Frank O'Mahony; C. Patrick Yue; Mark Horowitz; S. Simon Wong (DAC, 2003)

On-Chip Interconnect Inductance - Friend or Foe (Invited). - S. Simon Wong; C. Patrick Yue; Richard Chang 003; So-Young Kim; Bendik Kleveland; Frank O'Mahony (ISQED, 2003)

A 10-GHz global clock distribution using coupled standing-wave oscillators. - Frank O'Mahony; C. Patrick Yue; Mark A. Horowitz; S. Simon Wong (IEEE J. Solid State Circuits, 2003)

A low-power, 20-Gb/s continuous-time adaptive passive equalizer. - Ruifeng Sun; Jaejin Park; Frank O'Mahony; C. Patrick Yue (ISCAS (2), 2005)

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. - Bryan Casper; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; K. Canagasaby; Joseph T. Kennedy; E. Yeung; Randy Mooney (ISSCC, 2006)

A 20Gb/s Embedded Clock Transceiver in 90nm CMOS. - Bryan Casper; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; K. Canagasaby; Joe Kennedy 001; Randy Mooney (ISSCC, 2006)

Strong injection locking of low-Q LC oscillators. - Mozhgan Mansuri; Frank O'Mahony; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Sudip Shekhar; Randy Mooney; Bryan Casper (CICC, 2008)

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. - Frank O'Mahony; Sudip Shekhar; Mozhgan Mansuri; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Bryan Casper; David J. Allstot; Randy Mooney (ISSCC, 2008)

A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. - Ganesh Balamurugan; Joseph T. Kennedy; Gaurab Banerjee; James E. Jaussi; Mozhgan Mansuri; Frank O'Mahony; Bryan Casper; Randy Mooney (IEEE J. Solid State Circuits, 2008)

A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. - Dong Hun Shin; Ji-Eun Jang; Frank O'Mahony; C. Patrick Yue (CICC, 2009)

Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links - A Tutorial. - Bryan Casper; Frank O'Mahony (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver. - Sudip Shekhar; Ganesh Balamurugan; David J. Allstot; Mozhgan Mansuri; James E. Jaussi; Randy Mooney; Joseph T. Kennedy; Bryan Casper; Frank O'Mahony (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Varactor-based signal restoration for near-speed-of-light surfing global interconnect. - Suwen Yang; Robert J. Drost; Mark R. Greenstreet; Shahriar Mirabbasi; Frank O'Mahony (CICC, 2010)

A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS. - Ganesh Balamurugan; Frank O'Mahony; Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Bryan Casper (ISSCC, 2010)

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. - Frank O'Mahony; Joseph T. Kennedy; James E. Jaussi; Ganesh Balamurugan; Mozhgan Mansuri; Clark Roberts; Sudip Shekhar; Randy Mooney; Bryan Casper (ISSCC, 2010)

A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. - Kangmin Hu; Tao Jiang 005; Jingguang Wang; Frank O'Mahony; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2010)

A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. - Frank O'Mahony; James E. Jaussi; Joseph T. Kennedy; Ganesh Balamurugan; Mozhgan Mansuri; Clark Roberts; Sudip Shekhar; Randy Mooney; Bryan Casper (IEEE J. Solid State Circuits, 2010)

An on-die all-digital delay measurement circuit with 250fs accuracy. - Mozhgan Mansuri; Bryan Casper; Frank O'Mahony (VLSIC, 2012)

Design considerations for low-power receiver front-end in high-speed data links. - Sudip Shekhar; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; Bryan Casper (CICC, 2013)

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. - Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Tzu-Chien Hsueh; Sudip Shekhar; Ganesh Balamurugan; Frank O'Mahony; Clark Roberts; Randy Mooney; Bryan Casper (ISSCC, 2013)

A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. - Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Tzu-Chien Hsueh; Sudip Shekhar; Ganesh Balamurugan; Frank O'Mahony; Clark Roberts; Randy Mooney; Bryan Casper (IEEE J. Solid State Circuits, 2013)

F6: Energy-efficient I/O design for next-generation systems. - Frank O'Mahony; Nicola Da Dalt; Ken Chang; Hisakatsu Yamaguchi; Chulwoo Kim; Elad Alon (ISSCC, 2014)

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. - Amr Elshazly; Ajay Balankutty; Yan-Yu Huang; Kai Yu 016; Frank O'Mahony (VLSIC, 2014)

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. - Ken Chang; Frank O'Mahony; Elad Alon; Hyeon-Min Bae; Nicola Da Dalt; Eric Fluhr (ISSCC, 2015)

10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. - Rajeev K. Dokania; Alexandra M. Kern; Mike He; Adam C. Faust; Richard Tseng; Skyler Weaver; Kai Yu 016; Christiaan Bil; Tao Liang; Frank O'Mahony (ISSCC, 2015)

EP3: Innovating on the tapeout treadmill. - Jack Kenney; Frank O'Mahony (ISSCC, 2015)

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. - Jihwan Kim; Ajay Balankutty; Amr Elshazly; Yan-Yu Huang; Hang Song; Kai Yu 016; Frank O'Mahony (ISSCC, 2015)

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements. - Tzu-Chien Hsueh; Frank O'Mahony; Mozhgan Mansuri; Bryan Casper (IEEE J. Solid State Circuits, 2015)

Session 23 overview: Electrical and optical link innovations. - Frank O'Mahony; Simone Erba (ISSCC, 2016)

Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O. - Ishita Mukhopadhyay; Mustansir Yunus Mukadam; Rajendran Narayanan; Frank O'Mahony; Alyssa B. Apsel (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Session 6 overview: Ultra-high-speed wireline. - Simone Erba; Takayuki Shibasaki; Frank O'Mahony (ISSCC, 2017)

Session 29 overview: Optical- and electrical-link innovations. - Samuel Palermo; Hideyuki Nosaka; Frank O'Mahony (ISSCC, 2017)

Session 16 overview: Advanced optical and wireline techniques: Wireline subcommittee. - Azita Emami; Andrew K. Joy; Frank O'Mahony (ISSCC, 2018)

A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Skyler Weaver; Kai Yu 016; Frank O'Mahony (ISSCC, 2018)

Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. - Mounir Meghelli; Hyeon-Min Bae; Frank O'Mahony (ISSCC, 2018)

Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. - Roberto Nonis; Pavan Kumar Hanumolu; Frank O'Mahony (ISSCC, 2018)

A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Dan Shi; Skyler Weaver; Kai Yu 016; Frank O'Mahony (IEEE J. Solid State Circuits, 2019)

8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. - Wilfred Gomes; Sanjeev Khushu; Doug B. Ingerly; Patrick N. Stover; Nasirul I. Chowdhury; Frank O'Mahony; Ajay Balankutty; Noam Dolev; Martin G. Dixon; Lei Jiang; Surya Prekke; Biswajit Patra; et al. (ISSCC, 2020)

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen Kim; Yutao Liu; Savyassachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (ISSCC, 2021)

A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. - Shiva Kiran; Ajay Balankutty; Yutao Liu; Rajeev Dokania; Hariprasath Venkataraman; Priya Wali; Stephen Kim; Yoel Krupnik; Ariel Cohen 001; Frank O'Mahony (VLSI Circuits, 2021)

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. - Wilfred Gomes; Altug Koker; Patrick N. Stover; Doug B. Ingerly; Scott Siers; Srikrishnan Venkataraman; Chris Pelto; Tejas Shah; Amreesh Rao; Frank O'Mahony; Eric Karl; Lance Cheney; et al. (ISSCC, 2022)

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen T. Kim; Yutao Liu; Savyasaachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (IEEE J. Solid State Circuits, 2022)

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. - Ahmad Khairi; Yoel Krupnik; Amir Laufer; Yoav Segal; Marco Cusmai; Itamar Levin; Ari Gordon; Yaniv Sabag; Vitali Rahinski; Idan Lotan; Gadi Ori; Noam Familia; et al. (IEEE J. Solid State Circuits, 2023)

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. - Jihwan Kim; Ariel Cohen 001; Mike Peng Li; Ajay Balankutty; Sandipan Kundu; Ahmad Khairi; Yoel Krupnik; Yoav Segal; Marco Cusmai; Dror Lazar; Ari Gordon; Noam Familia; et al. (CICC, 2024)