Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. - Frank Poehl; Walter Anheier (J. Electron. Test., 1999)

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. - Frank Poehl; Matthias Beck; Ralf Arnold; Peter Muhmenthaler; Nagesh Tamarapalli; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2003)

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. - Matthias Beck; Olivier Barondeau; Martin Kaibel; Frank Poehl; Xijiang Lin; Ron Press (DATE, 2005)

Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. - Matthias Beck; Olivier Barondeau; Frank Poehl; Xijiang Lin; Ron Press (VTS, 2005)

On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture. - Frank Poehl; Jan Rzeha; Matthias Beck; Michael Gössel; Ralf Arnold; Peter Ossimitz (ETS, 2006)

On-chip evaluation, compensation and storage of scan diagnosis data. - Frank Poehl; Matthias Beck; Ralf Arnold; Jan Rzeha; Thomas Rabenalt; Michael Gössel (IET Comput. Digit. Tech., 2007)

Production test challenges for highly integrated mobile phone SOCs - A case study. - Frank Poehl; Frank Demmerle; Juergen Alt; Hermann Obermeir (ETS, 2010)

Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique. - Thomas Rabenalt; Michael Richter 002; Frank Poehl; Michael Gössel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)