WiCkeD: analog circuit synthesis incorporating mismatch. - Kurt Antreich; Josef Eckmüller; Helmut Graeb; Michael Pronath; Frank Schenkel; Robert Schwencker; Stephan Zizala (CICC, 2000)

The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. - Robert Schwencker; Frank Schenkel; Helmut E. Graeb; Kurt Antreich (DATE, 2000)

A fast method for identifying matching-relevant transistor pairs. - Frank Schenkel; Michael Pronath; Helmut Graeb; Kurt Antreich (CICC, 2001)

Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. - Frank Schenkel; Michael Pronath; Stephan Zizala; Robert Schwencker; Helmut E. Graeb; Kurt Antreich (DAC, 2001)

Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. - Robert Schwencker; Frank Schenkel; Michael Pronath; Helmut E. Graeb (DATE, 2002)

Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. - Guido Stehr; Michael Pronath; Frank Schenkel; Helmut E. Graeb; Kurt Antreich (ICCAD, 2003)

A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models. - Benjamin Prautsch; Thomas Markwirth; Frank Schenkel; Reimund Wittmann; Uwe Eichler; Jens Lienig (SMACD, 2022)