Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. - Yves Bertrand; Frédéric Bancel; Michel Renovell (ITC, 1993)

A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. - Yves Bertrand; Frédéric Bancel; Michel Renovell (VLSI Design, 1993)

Scan Design and Secure Chip. - David Hély; Marie-Lise Flottes; Frédéric Bancel; Bruno Rouzeyre; Nicolas Bérard; Michel Renovell (IOLTS, 2004)

Test control for secure scan designs. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2005)

Integration of Reconfigurable Logic on Secure Circuits. - Nicolas Valette; Lionel Torres; Frédéric Bancel; Nicolas Bérard (ReCoSoC, 2005)

A secure scan design methodology. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (DATE, 2006)

Secure Scan Techniques: A Comparison. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2006)

Securing embedded programmable gate arrays in secure circuits. - Nicolas Valette; Lionel Torres; Gilles Sassatelli; Frédéric Bancel (IPDPS, 2006)

Scan Pattern Watermarking. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (LATW, 2006)

Robustness of circuits under delay-induced faults : test of AES with the PAFI tool. - Olivier Faurax; Assia Tria; Laurent Freund; Frédéric Bancel (IOLTS, 2007)

Securing Scan Control in Crypto Chips. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (J. Electron. Test., 2007)