An Auto-adaptative Reconfigurable Architecture for the Control. - Nicolas Ventroux; Stéphane Chevobbe; Frédéric Blanc 001; Thierry Collette (Asia-Pacific Computer Systems Architecture Conference, 2004)

Advances in Practical Implementation of the Digital Media Processing: Towards Reconfigurable Computation. - Eva Dokládalová; Stéphane Chevobbe; Frédéric Blanc 001 (EWIMT, 2004)

RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems. - Stéphane Chevobbe; Nicolas Ventroux; Frédéric Blanc 001; Thierry Collette (SAMOS, 2004)

A Low Complex Scheduling Algorithm for Multi-processor System-on-Chip. - Nicolas Ventroux; Frédéric Blanc 001; Dominique Lavenier (Parallel and Distributed Computing and Networks, 2005)

Control Unit for Parallel Embedded System. - Stéphane Chevobbe; Raphaël David; Frédéric Blanc 001; Thierry Collette; Olivier Sentieys (ReCoSoC, 2006)

A Heuristic (delta, D) Digraph to Interpolate between Hypercube and de Bruijn Topologies for Future On-Chip Interconnection Networks. - Samer Damaj; Thierry Goubier; Frédéric Blanc 001; Bernard Pottier (ICPP Workshops, 2009)

Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor. - Pascal Aubry; Pierre-Edouard Beaucamps; Frédéric Blanc 001; Bruno Bodin; Sergiu Carpov; Loïc Cudennec; Vincent David; Philippe Dore; Paul Dubrulle; Benoît Dupont de Dinechin; François Galea; Thierry Goubier; et al. (ICCS, 2013)

Demo: MPPA® manycore processor towards future ADAS system solutions. - Pierre-Edouard Beaucamps; Frédéric Blanc Kalray (DASIP, 2016)