Design for millimeter-wave applications in silicon technologies. - Andreia Cathelin; Baudouin Martineau; N. Seller; S. Douyere; Jean Gorisse; Sébastien Pruvost; Christine Raynaud; Frederic Gianesello; Sébastien Montusclat; Sorin P. Voinigescu; Ali M. Niknejad; Didier Belot; et al. (ESSCIRC, 2007)

80 GHz low noise amplifiers in 65nm CMOS SOI. - Baudouin Martineau; Andreia Cathelin; François Danneville; Andreas Kaiser; Gilles Dambrine; Sylvie Lépilliet; Frederic Gianesello; Didier Belot (ESSCIRC, 2007)

A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS. - Baudouin Martineau; Vincent Knopik; Alexandre Siligaris; Frederic Gianesello; Didier Belot (ISSCC, 2010)

A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining. - Jiashu Chen; Lu Ye; Diane Titz; Fred Gianesello; Romain Pilard; Andreia Cathelin; Fabien Ferrero; Cyril Luxey; Ali M. Niknejad (ISSCC, 2013)

30 dBm P1dB and 4 dB insertion losses optimized 4G antenna tuner fully integrated in a 130 nm CMOS SOI technology. - Florence Sonnerat; Romain Pilard; Frederic Gianesello; Sebastien Jan; François Le Pennec; Christian Person; Cedric Durand; Daniel Gloria (RWS, 2013)

17.8 A compact 130GHz fully packaged point-to-point wireless system with 3D-printed 26dBi lens antenna achieving 12.5Gb/s at 1.55pJ/b/m. - Nemat Dolatsha; Baptiste Grave; Mahmoud Sawaby; Cheng Chen; Afshin Babveyh; Siavash Kananian; Aimeric Bisognin; Cyril Luxey; Frederic Gianesello; Jorge R. Costa; Carlos Fernandes 001; Amin Arbabian (ISSCC, 2017)

A 94-GHz 4TX-4RX Phased-Array FMCW Radar Transceiver With Antenna-in-Package. - Andrew Townley; Paul Swirhun; Diane Titz; Aimeric Bisognin; Frederic Gianesello; Romain Pilard; Cyril Luxey; Ali M. Niknejad (IEEE J. Solid State Circuits, 2017)

Session 21 overview: Extending silicon and its applications: Technology directions subcommittee. - Jan Genoe; Frederic Gianesello; Makoto Nagata (ISSCC, 2018)

F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. - Bo Zhang; Frederic Gianesello; Simone Erba; Mounir Meghelli; Azita Emami; Takayuki Shibasaki (ISSCC, 2018)

Smart Way to Adjust Schottky Barrier Height in 130 nm BiCMOS Process for sub-THz Applications. - Vincent Gidel; Frédéric Gianesello; Pascal Chevalier 002; Grégory Avenier; Nicolas Guitard; Michel Buczko; Cyril Luxey; Guillaume Ducournau (RWS, 2020)

Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions Subcommittee. - Sriram R. Vangal; Long Yan; Frederic Gianesello (ISSCC, 2021)

Notched gate MOSFET for capacitance reduction in RF SOI technology. - Lucas Antunes Tambara; Pascal Masson; Julien Amouroux; Stéphane Monfray; Julien Dura; Frederic Gianesello; Julien Babic; Romain Debroucke; Loic Welter; Siddhartha Dhar; Bernadette Gros; Clement Charbuillet; et al. (DTTIS, 2023)

Improving off-state capacitance of SOI-CMOS RF switches: how good are air microcavities? - Daniel Gheysens; Alain Fleury; Stéphane Monfray; Frédéric Gianesello; Philippe Cathelin; Jean-François Robillard; David Troadec; Emmanuel Dubois 002 (ESSDERC, 2023)