Frederic T. Chong

According to our database1, Frederic T. Chong authored at least 118 papers between 1992 and 2019.

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2019
Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM.
IEEE Trans. Computers, 2019

Formal constraint-based compilation for noisy intermediate-scale quantum systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Resource optimized quantum architectures for surface code implementations of magic-state distillation.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Asymptotic improvements to quantum circuits via qutrits.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Protecting Page Tables from RowHammer Attacks using Monotonic Pointers in DRAM True-Cells.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Data Center Energy Efficiency.
Proceedings of the Encyclopedia of Database Systems, Second Edition, 2018

Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Cooperative NV-NUMA: prolonging non-volatile memory lifetime through bandwidth sharing.
Proceedings of the International Symposium on Memory Systems, 2018

Charm: A Language for Closed-Form High-Level Architecture Modeling.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Quantum Computing is Getting Real: Architecture, PL, and OS Roles in Closing the Gap between Quantum Algorithms and Machines.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Quantum Computing and Irregular Applications.
Proceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms, 2017

Optimized surface code communication in superconducting quantum computers.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Memory cocktail therapy: a general learning-based framework to optimize dynamic tradeoffs in NVMs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures.
Proceedings of the International Symposium on Memory Systems, 2017

Predicting memory page stability and its application to memory deduplication and live migration.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Challenging on-chip SRAM security with boot-state statistics.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016
IMR: High-Performance Low-Cost Multi-Ring NoCs.
IEEE Trans. Parallel Distrib. Syst., 2016

Impact of Future Technologies on Architecture.
IEEE Micro, 2016

Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
ScaffCC: Scalable compilation and analysis of quantum programs.
Parallel Computing, 2015

Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data Expansion.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Compiler Management of Communication and Parallelism for Quantum Computation.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Networks on Chip with Provable Security Properties.
IEEE Micro, 2014

Data Center Energy Efficiency: Improving Energy Efficiency in Data Centers Beyond Technology Scaling.
IEEE Design & Test, 2014

Bridging the energy-efficiency gap in a future of massive data.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

ReDHiP: Recalibrating Deep Hierarchy Prediction for Energy Efficiency.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Characterizing the performance effect of trials and rotations in applications that use Quantum Phase Estimation.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

ScaffCC: a framework for compilation and analysis of quantum computing programs.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

Sapper: a language for hardware-level security policy enforcement.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Special Issue: Selected papers from the 2012 IEEE International Green Computing Conference (IGCC 2012).
SUSCOM, 2013

Position paper: Sapper - a language for provable hardware policy enforcement.
Proceedings of the 2013 ACM SIGPLAN Workshop on Programming Languages and Analysis for Security, 2013

SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

QuRE: The Quantum Resource Estimator toolbox.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Memristors for neural branch prediction: a case study in strict latency and write endurance challenges.
Proceedings of the Computing Frontiers Conference, 2013

A Case for Energy-Aware Security Mechanisms.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012
Barely alive memory servers: Keeping data active in a low-power state.
JETC, 2012

A Study of Reusing Smartphones to Augment Elementary School Education.
IJHCR, 2012

Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Building Technologies that Help Cyber-Defense: Hardware-enabled Trust.
Proceedings of the ISSE 2012, 2012

LogStore: toward energy-proportional storage servers.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Power-Aware Resource Allocation for CPU- and Memory-Intense Internet Services.
Proceedings of the Energy Efficient Data Centers - First International Workshop, 2012

2011
Quantum Computing for Computer Architects, Second Edition
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2011

Caisson: a hardware description language for secure information flow.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Exploiting Data Similarity to Reduce Memory Footprints.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Gate-Level Information-Flow Tracking for Secure Architectures.
IEEE Micro, 2010

Secure information flow analysis for hardware design: using the right abstraction for the job.
Proceedings of the 2010 Workshop on Programming Languages and Analysis for Security, 2010

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Smartphone Evolution and Reuse: Establishing a More Sustainable Model.
Proceedings of the 39th International Conference on Parallel Processing, 2010

A case for smartphone reuse to augment elementary school education.
Proceedings of the International Green Computing Conference 2010, 2010

Quantifying the environmental advantages of large-scale computing.
Proceedings of the International Green Computing Conference 2010, 2010

Function flattening for lease-based, information-leak-free systems.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Putting Trojans on the Horns of a Dilemma: Redundancy for Information Theft Detection.
Trans. Computational Science, 2009

Execution leases: a hardware-supported mechanism for enforcing strong non-interference.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Conflict-Avoidance in Multicore Caching for Data-Similar Executions.
Proceedings of the 10th International Symposium on Pervasive Systems, 2009

Multi-execution: multicore caching for data-similar executions.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Complete information flow tracking from the gates up.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008
High-level interconnect model for the quantum logic array architecture.
JETC, 2008

Exploring the Processor and ISA Design for Wireless Sensor Network Applications.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Bezoar: Automated virtual machine-based full-system recovery from control-flow hijacking attacks.
Proceedings of the IEEE/IFIP Network Operations and Management Symposium: Pervasive Management for Ubioquitous Networks and Services, 2008

From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Credit-based dynamic reliability management using online wearout detection.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture.
Trans. HiPEAC, 2007

Life Cycle Aware Computing: Reusing Silicon Technology.
IEEE Computer, 2007

Design-space exploration of fault-tolerant building blocks for large-scale quantum computing.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

A pageable, defect-tolerant nanoscale memory system.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Quantum Computing for Computer Architects
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2006

Minos: Architectural support for protecting control data.
TACO, 2006

Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications.
J. Embedded Computing, 2006

Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Characterization of Error-Tolerant Applications when Protecting Control Data.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

A Realizable Distributed Ion-Trap Quantum Computer.
Proceedings of the High Performance Computing, 2006

Tile size selection for low-power tile-based architectures.
Proceedings of the Third Conference on Computing Frontiers, 2006

ExecRecorder: VM-based full-system replay for attack analysis and system recovery.
Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, 2006

Temporal search: detecting hidden malware timebombs with virtual machines.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
A security assessment of the minos architecture.
SIGARCH Computer Architecture News, 2005

Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era.
IEEE Design & Test of Computers, 2005

Experiences Using Minos as a Tool for Capturing and Analyzing Novel Worms for Unknown Vulnerabilities.
Proceedings of the Detection of Intrusions and Malware, 2005

On deriving unknown vulnerabilities from zero-day polymorphic and metamorphic worm exploits.
Proceedings of the 12th ACM Conference on Computer and Communications Security, 2005

2004
Datapath and control for quantum wires.
TACO, 2004

Ions, atoms, and bits: An architectural approach to quantum computing.
Advances in Computers, 2004

Efficient orchestration of sub-word parallelism in media processors.
Proceedings of the SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2004

Minos: Control Data Attack Prevention Orthogonal to Memory Model.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003
Cache Coherence in Intelligent Memory Systems.
IEEE Trans. Computers, 2003

The effect of communication costs in solid-state quantum computing architectures.
Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Building Quantum Wires: The Long and the Short of It.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Hardware-software co-design of embedded sensor-actuator networks.
SIGARCH Computer Architecture News, 2002

Operating Systems Techniques for Parallel Computation in Intelligent Memory.
Parallel Processing Letters, 2002

Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.
J. Instruction-Level Parallelism, 2002

A Practical Architecture for Reliable Quantum Computers.
IEEE Computer, 2002

HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.
Proceedings of the High Performance Computing, 2002

2000
Algorithmic Complexity with Page-Based Intelligent Memory.
Parallel Processing Letters, 2000

HLS: combining statistical and symbolic simulation to guide microprocessor designs.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Reducing Cost and Tolerating Defects in Page-based Intelligent Memory.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Shared Memory Versus Message Passing for Iterative Solution of Sparse Irregular Problems.
Parallel Processing Letters, 1999

Exploiting ILP in Page-based Intelligent Memory.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

ActiveOS: Virtualizing Intelligent Memory.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Active Pages: A Computation Model for Intelligent Memory.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

The Sensitivity of Communication Mechanisms to Bandwidth and Latency.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1997
parallel communication mechanisms for sparse, irregular applications.
PhD thesis, 1997

1996
Application Performance on the MIT Alewife Machine.
IEEE Computer, 1996

1995
Multiprocessor Runtime Support for Fine-Grained, Irregular Dags.
Parallel Processing Letters, 1995

Remote Queues: Exposing Message Queues for Optimization and Atomicity.
Proceedings of the 7th Annual ACM Symposium on Parallel Algorithms and Architectures, 1995

1994
Scalable expanders: exploiting hierarchical random wiring.
Proceedings of the Twenty-Sixth Annual ACM Symposium on Theory of Computing, 1994

Packaging and Multiplexing of Hierarchical Scalable Expanders.
Proceedings of the Parallel Computer Routing and Communication, 1994

Building a better butterfly: the multiplexed metabutterfly.
Proceedings of the International Symposium on Parallel Architectures, 1994

METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1992
Design and Performance of Multipath MIN Architectures.
Proceedings of the 4th Annual ACM Symposium on Parallel Algorithms and Architectures, 1992


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