A program-driven simulation model of an MIMD multiprocessor. - Fredrik Dahlgren (Annual Simulation Symposium, 1991)

A Lockup-Free Multiprocessor Cache Design. - Per Stenström; Fredrik Dahlgren; Lars Lundberg (ICPP (1), 1991)

On Reconfigurable On-Chip Data Caches. - Fredrik Dahlgren; Per Stenström (MICRO, 1991)

The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors. - Mats Brorsson; Fredrik Dahlgren; Håkan Nilsson; Per Stenström (Annual Simulation Symposium, 1993)

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (ICPP (1), 1993)

Reducing the Write Traffic for a Hybrid Cache Protocol. - Fredrik Dahlgren; Per Stenström (ICPP (1), 1994)

Combined Performance Gains of Simple Cache Protocol Extensions. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (ISCA, 1994)

Using hints to reduce the read miss penalty for flat COMA protocols. - Mårten Björkman; Fredrik Dahlgren; Per Stenström (HICSS (1), 1995)

Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. - Fredrik Dahlgren; Per Stenström (HPCA, 1995)

Boosting the Performance of Hybrid Snooping Cache Protocols. - Fredrik Dahlgren (ISCA, 1995)

Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. - Fredrik Dahlgren; Per Stenström (J. Parallel Distributed Comput., 1995)

Sequential Hardware Prefetching in Shared-Memory Multiprocessors. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (IEEE Trans. Parallel Distributed Syst., 1995)

Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. - Anders Landin; Fredrik Dahlgren (HPCA, 1996)

Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). - Per Stenström; Fredrik Dahlgren (Computer, 1996)

Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. - Fredrik Dahlgren; Per Stenström (IEEE Trans. Parallel Distributed Syst., 1996)

Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors. - Fredrik Dahlgren; Anders Landin (HPCA, 1997)

Reducing the Read-Miss Penalty for Flat COMA Protocols. - Fredrik Dahlgren; Per Stenström; Mårten Björkman (Comput. J., 1997)

Boosting the Performance of Shared Memory Multiprocessors. - Per Stenström; Mats Brorsson; Fredrik Dahlgren; Håkan Grahn; Michel Dubois 001 (Computer, 1997)

The Sensitivity of Communication Mechanisms to Bandwidth and Latency. - Frederic T. Chong; Rajeev Barua; Fredrik Dahlgren; John Kubiatowicz; Anant Agarwal (HPCA, 1998)

SimICS/Sun4m: A Virtual Workstation. - Peter S. Magnusson; Fredrik Larsson; Andreas Moestedt; Bengt Werner; Jim Nilsson; Per Stenström; Fredrik Lundholm; Magnus Karlsson 002; Fredrik Dahlgren; Håkan Grahn (USENIX ATC, 1998)

A holistic approach to computer system design education based on system simulation techniques. - Per Stenström; Fredrik Dahlgren (WCAE@ISCA, 1998)

An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols. - Fredrik Dahlgren; Jonas Skeppstedt; Per Stenström (Future Gener. Comput. Syst., 1998)

Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. - Fredrik Dahlgren; Michel Dubois 001; Per Stenström (IEEE Trans. Computers, 1998)

Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. - Jim Nilsson; Fredrik Dahlgren (ICPP, 1999)

Efficient management of memory hierarchies in embedded DRAM systems. - Ashley Saulsbury; Su-Jaen Huang; Fredrik Dahlgren (International Conference on Supercomputing, 1999)

Cache-Only Memory Architectures. - Fredrik Dahlgren; Josep Torrellas (Computer, 1999)

Techniques for Improving Performance of Hybrid Snooping Cache Protocols. - Fredrik Dahlgren (J. Parallel Distributed Comput., 1999)

Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. - Jonas Skeppstedt; Fredrik Dahlgren; Per Stenström (J. Parallel Distributed Comput., 1999)

A Prefetching Technique for Irregular Accesses to Linked Data Structures. - Magnus Karlsson 002; Fredrik Dahlgren; Per Stenström (HPCA, 2000)

Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. - Martin Kämpe; Fredrik Dahlgren (IPDPS, 2000)

Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors. - Jim Nilsson; Fredrik Dahlgren (IPDPS, 2000)

Recency-based TLB preloading. - Ashley Saulsbury; Fredrik Dahlgren; Per Stenström (ISCA, 2000)

Topic 08+13: Instruction-Level Parallelism and Computer Architecture. - Eduard Ayguadé; Fredrik Dahlgren; Christine Eisenbeis; Roger Espasa; Guang R. Gao; Henk L. Muller; Rizos Sakellariou; André Seznec (Euro-Par, 2001)

Future Mobile Phones - Complex Design Challenges from an Embedded Systems Perspective. - Fredrik Dahlgren (ICECCS, 2001)

TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. - Magnus Ekman; Per Stenström; Fredrik Dahlgren (ISLPED, 2002)

Computability and continuity in metric partial algebras equipped with computability structures. - Fredrik Dahlgren (Math. Log. Q., 2004)

Partial Continuous Functions and Admissible Domain Representations. - Fredrik Dahlgren (J. Log. Comput., 2007)

Effective Distribution Theory. - Fredrik Dahlgren (2007)

HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. - Angelos Arelakis; Fredrik Dahlgren; Per Stenström (MICRO, 2015)