Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS. - Tao Jiang 005; Wing Liu; Freeman Y. Zhong; Charlie Zhong; Patrick Yin Chiang (CICC, 2010)

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS. - Tao Jiang 005; Wing Liu; Freeman Y. Zhong; Charlie Zhong; Kangmin Hu; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2012)

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS. - Hao Li 047; Shuai Chen; Liqiong Yang; Rui Bai 001; Weiwu Hu; Freeman Y. Zhong; Samuel Palermo; Patrick Yin Chiang (VLSIC, 2014)