A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). - Friedel Gerfers; Yiannos Manoli (ISLPED, 2000)

A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. - Friedel Gerfers; Yiannos Manoli (DATE, 2001)

Clock jitter insensitive continuous-time ΣΔ modulators. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (ICECS, 2001)

Successful design of cascaded continuous-time ΣΔ modulators. - Maurits Ortmanns; Friedel Gerfers; Lourans Samid; Yiannos Manoli (ICECS, 2001)

On the synthesis of cascaded continuous-time Sigma-Delta modulators. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (ISCAS (5), 2001)

Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators. - Friedel Gerfers; Kian Min Soh; Maurits Ortmanns; Yiannos Manoli (ISCAS (4), 2002)

Multirate cascaded continuous time Sigma-Delta modulators. - Maurits Ortmanns; Lourans Samid; Yiannos Manoli; Friedel Gerfers (ISCAS (4), 2002)

A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator. - Lourans Samid; Maurits Ortmanns; Yiannos Manoli; Friedel Gerfers (ISCAS (3), 2002)

A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (ESSCIRC, 2003)

A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time ΣΔ modulators. - Friedel Gerfers; Maurits Ortmanns; P. Schmitz; Yiannos Manoli; Kian Min Soh (ICECS, 2003)

Compensation of the influence of finite gain-bandwidth on continuous-time sigma-delta modulators. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (ICECS, 2003)

A 1 V, 12-bit wideband continuous-time ΣΔ modulator for UMTS applications. - Friedel Gerfers; Maurits Ortmanns; Yiannos Manoli (ISCAS (1), 2003)

Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (ISCAS (1), 2003)

Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (ISCAS (1), 2003)

A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator. - Friedel Gerfers; Maurits Ortmanns; Yiannos Manoli (IEEE J. Solid State Circuits, 2003)

Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators. - Friedel Gerfers; Maurits Ortmanns; Yiannos Manoli (ISCAS (1), 2004)

A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators. - Matthias Keller; Yiannos Manoli; Friedel Gerfers (ISCAS (1), 2004)

A cascaded continuous-time Sigma Delta modulator with 80 dB dynamic range. - Maurits Ortmanns; Markus Kuderer; Yiannos Manoli; Friedel Gerfers (ISCAS (1), 2004)

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A new technique for automatic error correction in Sigma-Delta modulators. - Friedel Gerfers; Maurits Ortmanns; Yiannos Manoli (ISCAS (3), 2005)

Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed. - Friedel Gerfers; Maurits Ortmanns; Yiannos Manoli (ISCAS (3), 2005)

A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator. - Maurits Ortmanns; Friedel Gerfers; Yiannos Manoli (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A transistor-based clock jitter insensitive DAC architecture. - Friedel Gerfers; Maurits Ortmanns; P. Schmitz (ISCAS, 2006)

An infinite-skew tolerant delay locked loop. - Pavel V. Petkov; Jim E. Conder; Friedel Gerfers (ISCAS, 2006)

On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma-Delta Modulators. - Matthias Keller; Alexander Buhmann; Friedel Gerfers; Maurits Ortmanns; Yiannos Manoli (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer. - Friedel Gerfers; Gerrit W. den Besten; Pavel V. Petkov; Jim E. Conder; Andreas J. Koellmann (IEEE J. Solid State Circuits, 2008)

A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. - Friedel Gerfers; Ramin Farjad-Rad; Michael Brown; Ahmad Tavakoli; David Nguyen; Hiok-Tiaq Ng; Ramin Shirani (ISSCC, 2012)

A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. - Ramin Farjad-Rad; Friedel Gerfers; Michael Brown; Ahmad Tavakoli; David Nguyen; Hossein Sedarat; Ramin Shirani; Hiok-Tiaq Ng (IEEE J. Solid State Circuits, 2012)

Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. - Adel Fatemi; Heinrich Klar; Friedel Gerfers (ISCAS, 2016)

Link-budget calculations for CMOS integrated microwave receivers. - Soenke Vehring; Yaoshun Ding; Dominic Maurath; Friedel Gerfers; Georg Böck (EUROCON, 2017)

High output power frequency doubler for digital PLLs in fully integrated 24 GHz CMOS radar systems. - Soenke Vehring; Yaoshun Ding; Philipp Scholz; Dominic Maurath; Friedel Gerfers; Georg Böck (ICUWB, 2017)

A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOS. - Hossein Ghafarian; Friedel Gerfers (ISCAS, 2017)

A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters. - Marcel Runge; Friedel Gerfers (ISCAS, 2017)

Analysis and compensation technique canceling non-linear switch and package impedance effects of a 3.2GS/S TX-DAC. - Hossein Ghafarian; Friedel Gerfers (MWSCAS, 2017)

Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC. - Marcel Runge; Dario Schmock; Friedel Gerfers (MWSCAS, 2017)

Channel analysis for a 6.4 Gb/s DDR5 data buffer receiver front-end. - Stefanie Lehmann; Friedel Gerfers (NEWCAS, 2017)

A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS. - Marcel Runge; Dario Schmock; Philipp Scholz; Georg Böck; Friedel Gerfers (ESSCIRC, 2018)

Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. - Marcel Runge; Friedel Gerfers (ISCAS, 2018)

AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs. - Nima Lotfi; Marcel Runge; Friedel Gerfers (MWSCAS, 2018)

Analysis of Package Impedance Effects on the Linearity of Source Series Terminated DACs. - Helia Ordouei; Hossein Ghafarian; Friedel Gerfers (MWSCAS, 2018)

A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. - Marcel Runge; Sebastian Linnhoff; Friedel Gerfers (MWSCAS, 2018)

Behavioral Model for a High-Speed 2: 1 Analog Multiplexer. - Christian Schmidt 001; Patrick Zielonka; Volker Jungnickel; Ronald Freund; Tobias Tannert; Markus Grozing; Manfred Berroth; Friedel Gerfers (MWSCAS, 2018)

Digital-to-Analog Converters Using Frequency Interleaving: Mathematical Framework and Experimental Verification. - Christian Schmidt 001; Christoph Kottke; Vicky H. Tanzil; Ronald Freund; Volker Jungnickel; Friedel Gerfers (Circuits Syst. Signal Process., 2018)

A CMOS-Based Electrochemical DNA Hybridization Microarray for Diagnostic Applications with 109 Test Sites. - Norman Dodel; Roland Thewes; Anouar Laifi; Dirk Eberhardt; Stefan Keil; Leonhard Sturm; Armin Klumpp; Oliver Freudenberg; Friedel Gerfers; Gerhard Hartwich (BioCAS, 2019)

High Performance Electronic Design Education - from Technology towards High Frequency Chip Sets. - Andreas Mai; Philipp Scholz; Gerhard G. Fischer; Friedel Gerfers (FIE, 2019)

Body-Bias Techniques in CMOS 22FDX® for Mixed-Signal Circuits and Systems. - Friedel Gerfers; Nima Lotfi; Enne Wittenhagen; Hossein Ghafarian; Yuan Tian 032; Marcel Runge (ICECS, 2019)

A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI. - Nima Lotfi; Pedro Lehmann Ibáñez; Marcel Runge; Friedel Gerfers (ISCAS, 2019)

Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs. - Marcel Runge; Nima Lotfi; Friedel Gerfers (ISCAS, 2019)

Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI. - Hossein Ghafarian; Helia Ordouei; Friedel Gerfers (MWSCAS, 2019)

An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI. - Nima Lotfi; Friedel Gerfers (NEWCAS, 2019)

A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network. - Paul Hollmann; Marcel Runge; Friedel Gerfers (ICECS, 2020)

A Transmission-Line-based Phase Shifter for High-Speed, Ultra-Low-Power N-PSK Transmitters. - Patrick Kurth; Kai Misselwitz; Urs Hecht; Friedel Gerfers (ICECS, 2020)

A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS. - Sebastian Linnhoff; Frowin Buballa; Michael Reinhold; Friedel Gerfers (ICECS, 2020)

Towards pW-Class IoT Nodes using Crystalline Oxide Semiconductor Dynamic Logic. - Tobias Kaiser; Friedel Gerfers (ISCAS, 2020)

A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX. - Marcel Runge; Dario Schmock; Enne Wittenhagen; Friedel Gerfers (ISCAS, 2020)

A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. - Suhas Shivapakash; Hardik Jain; Olaf Hellwich; Friedel Gerfers (ISCAS, 2020)

A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio. - Enne Wittenhagen; Marcel Runge; Wilhelm Keusgen; Friedel Gerfers (ISCAS, 2020)

Up to 30-Fold BER Improvement using a Data-Dependent FFE Switching Technique for 112Gbit/s PAM-4 VCSEL Based Links. - Urs Hecht; Nikolay Ledentsov Jr.; Lukasz Chorchos; Patrick Kurth; Nikolay N. Ledentsov; Friedel Gerfers (OFC, 2020)

Optical Interconnects using Single-Mode and Multi-Mode VCSEL and Multi-Mode Fiber. - Nikolay N. Ledentsov; V. A. Shchukin; Vladimir P. Kalosha; Nikolay Ledentsov Jr.; Lukasz Chorchos; Jaroslaw P. Turkiewicz; Urs Hecht; Patrick Kurth; Friedel Gerfers; Justin Lavrencik; Siddharth Varughese; Stephen E. Ralph (OFC, 2020)

A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. - Marcel Runge; Julius Edler; Tobias Kaiser; Friedel Gerfers (CICC, 2021)

A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS. - Marcel Runge; Dario Schmock; Tobias Kaiser; Friedel Gerfers (CICC, 2021)

A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. - Frowin Buballa; Sebastian Linnhoff; Michael Reinhold; Friedel Gerfers (ISCAS, 2021)

A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers. - Patrick Kurth; Kai Misselwitz; Urs Hecht; Friedel Gerfers (ISCAS, 2021)

A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. - Sebastian Linnhoff; Erik Sippel; Frowin Buballa; Michael Reinhold; Martin Vossiek; Friedel Gerfers (ISCAS, 2021)

A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS. - Julius Edler; Marcel Runge; Friedel Gerfers (MWSCAS, 2021)

A Divider-less Automatic Frequency Calibration for Millimeter-Wave Sub-Sampling Phase-Locked Loops. - Patrick Kurth; Urs Hecht; Enne Wittenhagen; Friedel Gerfers (MWSCAS, 2021)

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). - Friedel Gerfers; Ping-Hsuan Hsieh; Dejan Markovic; Jun Deguchi; Eric Karl (IEEE J. Solid State Circuits, 2021)

A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. - Suhas Shivapakash; Hardik Jain; Olaf Hellwich; Friedel Gerfers (IEEE Open J. Circuits Syst., 2021)

FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons. - Simon Wiedemann; Suhas Shivapakash; Daniel Becking; Pablo Wiedemann; Wojciech Samek; Friedel Gerfers; Thomas Wiegand 001 (IEEE Open J. Circuits Syst., 2021)

Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®. - Enne Wittenhagen; Marcel Runge; Nima Lotfi; Hossein Ghafarian; Yuan Tian 032; Friedel Gerfers (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA. - Tobias Kaiser; Friedel Gerfers (ARCS, 2022)

A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. - Marcel Runge; Julius Edler; Dario Schmock; Tobias Kaiser; Friedel Gerfers (CICC, 2022)

Characterization of Multi-Gigabit Automotive Ethernet Channel Radiated Emissions in Relation to ECU PCB Shield-Ground Implementations. - Jamila Josip Borda; Kirsten Matheus; Friedel Gerfers (ETFA, 2022)

A Divider-less General PLL Lock Assist and Automatic Frequency Calibration System for Millimeter-Wave Sub-Sampling Phase-Locked Loops. - Patrick Kurth; Philipp Nickel; Urs Hecht; Friedel Gerfers (ICECS 2022, 2022)

A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC. - Kai Misselwitz; Marcel Runge; Friedel Gerfers (ICECS 2022, 2022)

A 224 Gbit/s Transceiver Front-end Design for Next Generation Data Centers. - Enne Wittenhagen; Urs Hecht; Halil Cirit; Saman Behtash; Srinivas Venkataram; Friedel Gerfers (ICECS 2022, 2022)

A TI 12 GS/s Sampled Beam-Forming Receiver for a $2 times 2$ Antenna-Array with 69 dBc SFDR. - Enne Wittenhagen; Patrick Kurth; Tobias Kaiser; Friedel Gerfers (ICECS 2022, 2022)

PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links. - Urs Hecht; Enne Wittenhagen; Halil Cirit; Saman Behtash; Srinivas Venkataram; Friedel Gerfers (ISCAS, 2022)

In-Vehicle Network Standards - Overview and Implementation Examples. - Helia Ordouei; Friedel Gerfers; Silvio Waldmann (ISCAS, 2022)

A novel OFDM-based Radar and Communication System Design using Digital IQ-Modulation and 52 GS/s Direct-RF Data Converter. - Silvio Waldmann; Helia Ordouei; Friedel Gerfers (ISCAS, 2022)

Beyond 10Gbps Electrical Automotive Ethernet Channel Insertion Loss Characterization. - Jamila Josip Borda; Kirsten Matheus; Friedel Gerfers (IV, 2022)

6G D-Band Receiver Model with High Spectral Efficiency Enabling Global System Optimization. - Patrick J. Artz; Friedel Gerfers (MWSCAS, 2022)

Sturdy-MASH Delta-Sigma Modulator with Improved Resolution Using Noise-coupling Multi-bit Quantizer. - Akif Omer Ucar; Friedel Gerfers (MWSCAS, 2022)

A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation. - Tobias Kaiser; Friedel Gerfers (COOL CHIPS, 2023)

True Voltage-Mode NRZ VCSEL Transmitter enabling 60 Gbit/s at 0.37 pJ/bit in 22 nm FDSOI. - Urs Hecht; Helia Ordouei; Nikolay Ledentsov Jr.; Philipp Scholz; Patrick Kurth; Nikolay N. Ledentsov; Friedel Gerfers (ESSCIRC, 2023)

25Gbps Automotive Ethernet: System PHY Characterization of ESD Based EM Interferences. - Jamila Josip Borda; Friedel Gerfers (ETFA, 2023)

Undersampling and SNR Degradation in Practical Direct RF Sampling Systems. - Dennis Osterland; Andreas Benzin; Friedel Gerfers; Giuseppe Caire (EuCNC/6G Summit, 2023)

A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. - Patrick Kurth; Urs Hecht; Frowin Buballa; Sebastian Linnhoff; Helia Ordouei; Friedel Gerfers (ISCAS, 2023)

A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs. - Helia Ordouei; Clirim Alija; Patrick Kurth; Friedel Gerfers (ISCAS, 2023)

A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS. - Frowin Buballa; Sebastian Linnhoff; Enne Wittenhagen; Urs Hecht; Friedel Gerfers (NEWCAS, 2023)

A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. - Sebastian Linnhoff; Frowin Buballa; Julius Edler; Enne Wittenhagen; Urs Hecht; Friedel Gerfers (NEWCAS, 2023)

A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS. - Enne Wittenhagen; Patrick Kurth; Urs Hecht; Frowin Buballa; Sebastian Linnhoff; Nima Lotfi; Friedel Gerfers (NEWCAS, 2023)

A 0.4 pJ/bit NRZ Voltage Mode VCSEL Driver for up to 224 Gbit/s SWDM Links. - Urs Hecht; Helia Ordouei; Nikolay Ledentsov Jr.; Philipp Scholz; Patrick Kurth; Ilya E. Titkov; Nikolay N. Ledentsov; Friedel Gerfers (OFC, 2023)

25Gbps Automotive Ethernet ECU PCB: MDI Design Implementation and Insertion Loss Characterization. - Jamila Josip Borda; Kirsten Matheus; Friedel Gerfers (VEHITS, 2023)

A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. - Julius Edler; Marcel Runge; Sebastian Linnhoff; Friedel Gerfers (VLSI Technology and Circuits, 2023)

An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter. - Marcel Runge; Julius Edler; Tobias Kaiser; Kai Misselwitz; Friedel Gerfers (IEEE J. Solid State Circuits, 2023)

A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator. - Patrick Kurth; Philipp Scholz; Philipp Nickel; Urs Hecht; Enne Wittenhagen; Kai Misselwitz; Friedel Gerfers (ISCAS, 2024)

A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SNDR in 22 nm CMOS FDSOI. - Kai Misselwitz; Friedel Gerfers (ISCAS, 2024)

An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. - Enne Wittenhagen; Dominik Wilding; Patrick Kurth; Sebastian Linnhoff; Frowin Buballa; Urs Hecht; Patrick J. Artz; Friedel Gerfers (ISCAS, 2024)

A Multiport Coaxial Interconnection for MTCA.4 Based High-Frequency Instrumentation Applications. - Johannes Zink 002; Frank Ludwig; Szymon Jablonski; Uros Mavric; Michael Fenner; Stanislav Chystiakov; Holger Schlarb; Friedel Gerfers (IEEE Trans. Instrum. Meas., 2024)

A DAC-based Transmitter with VCSEL Bias-Current Generation enabling 180 Gbit/s PAM-8 Electrical and 100 Gbit/s PAM-4 VCSEL-based Transmission in 22nm SOI. - Urs Hecht; Philipp Scholz; Patrick Kurth; Frowin Buballa; Helia Ordouei; Friedel Gerfers (CICC, 2025)

Halfbex: A RISC-V Microarchitecture with Narrow Data Path for Improved Energy Efficiency. - Äantas Kesten; Tobias Kaiser; Jenny Lichtenstein; Christian Rudorf; Friedel Gerfers (ISCAS, 2025)

A Wideband Open-Loop Residue Amplifier for a 7-bit 10GS/s Two-Step Flash ADC in 22nm SOI CMOS Process. - Jenny Lichtenstein; Äantas Kesten; Friedel Gerfers (ISCAS, 2025)

A Nyquist-rate 128 GS/s 6-Bit 64x Time-Interleaved SAR ADC in 22nm FD-SOI. - Christian Rudorf; Nima Lotfi; Sebastian Linnhoff; Enne Wittenhagen; Äantas Kesten; Friedel Gerfers (ISCAS, 2025)

Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability. - Tobias Kaiser; Esther Gottschalk; Kai Biethahn; Friedel Gerfers (IEEE Open J. Circuits Syst., 2025)