A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS. - Sebastian Linnhoff; Frowin Buballa; Michael Reinhold; Friedel Gerfers (ICECS, 2020)

A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. - Frowin Buballa; Sebastian Linnhoff; Michael Reinhold; Friedel Gerfers (ISCAS, 2021)

A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. - Sebastian Linnhoff; Erik Sippel; Frowin Buballa; Michael Reinhold; Martin Vossiek; Friedel Gerfers (ISCAS, 2021)

A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. - Patrick Kurth; Urs Hecht; Frowin Buballa; Sebastian Linnhoff; Helia Ordouei; Friedel Gerfers (ISCAS, 2023)

A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS. - Frowin Buballa; Sebastian Linnhoff; Enne Wittenhagen; Urs Hecht; Friedel Gerfers (NEWCAS, 2023)

A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. - Sebastian Linnhoff; Frowin Buballa; Julius Edler; Enne Wittenhagen; Urs Hecht; Friedel Gerfers (NEWCAS, 2023)

A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS. - Enne Wittenhagen; Patrick Kurth; Urs Hecht; Frowin Buballa; Sebastian Linnhoff; Nima Lotfi; Friedel Gerfers (NEWCAS, 2023)

An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. - Enne Wittenhagen; Dominik Wilding; Patrick Kurth; Sebastian Linnhoff; Frowin Buballa; Urs Hecht; Patrick J. Artz; Friedel Gerfers (ISCAS, 2024)

A DAC-based Transmitter with VCSEL Bias-Current Generation enabling 180 Gbit/s PAM-8 Electrical and 100 Gbit/s PAM-4 VCSEL-based Transmission in 22nm SOI. - Urs Hecht; Philipp Scholz; Patrick Kurth; Frowin Buballa; Helia Ordouei; Friedel Gerfers (CICC, 2025)