Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. - Fu-Wei Chen; Yi-Yu Liu (DATE, 2008)

Performance-driven dual-rail insertion for chip-level pre-fabricated design. - Fu-Wei Chen; Yi-Yu Liu (DATE, 2009)

Buffer design and optimization for lut-based structured ASIC design styles. - Po-Yang Hsu; Shu-Ting Lee; Fu-Wei Chen; Yi-Yu Liu (ACM Great Lakes Symposium on VLSI, 2009)

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. - Fu-Wei Chen; Yi-Yu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A physical-location-aware fault redistribution for maximum IR-drop reduction. - Fu-Wei Chen; Shih-Liang Chen; Yung-Sheng Lin; TingTing Hwang (ASP-DAC, 2011)

Clock tree synthesis with methodology of re-use in 3D IC. - Fu-Wei Chen; TingTing Hwang (DAC, 2012)

A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. - Fu-Wei Chen; Shih-Liang Chen; Yung-Sheng Lin; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Fault-tolerant TSV by using scan-chain test TSV. - Fu-Wei Chen; Hui-Ling Ting; TingTing Hwang (ASP-DAC, 2014)

Clock-Tree Synthesis with Methodology of Reuse in 3D-IC. - Fu-Wei Chen; TingTing Hwang (ACM J. Emerg. Technol. Comput. Syst., 2014)

Crosstalk-aware TSV-buffer Insertion in 3D IC. - Yen-Hao Chen; Po-Chen Huang; Fu-Wei Chen; Allen C.-H. Wu; TingTing Hwang (SoCC, 2019)