An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

The stabilized reference-line (SRL) technique for scaled DRAMs. - Kenji Tsuchida; Yukihito Oowaki; Masako Ohta; Daisaburo Takashima; Shigeyoshi Watanabe; Kazuya Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A high-density NAND EEPROM with block-page programming for microcomputer applications. - Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Yasuo Itoh; Ryozo Nakayama; Ryouhei Kirisawa; Seiichi Aritome; Tetsuo Endoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 4 Mb NAND EEPROM with tight programmed Vt distribution. - Masaki Momodomi; Tomoharu Tanaka; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Yasuo Itoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Reliability issues of flash memory cells. - Seiichi Aritome; Riichiro Shirota; Gertjan Hemink; Tetsuo Endoh; Fujio Masuoka (Proc. IEEE, 1993)

An experimental DRAM with a NAND-structured cell. - Takehiro Hasegawa; Daisaburo Takashima; Ryu Ogiwara; Masako Ohta; Shinichiro Shiratake; Takeshi Hamamoto; Takashi Yamada; Masami Aoki; Shigeru Ishibashi; Yukihito Oowaki; Shigeyoshi Watanabe; Fujio Masuoka (IEEE J. Solid State Circuits, 1993)

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. - Tomoharu Tanaka; Yoshiyuki Tanaka; Hiroshi Nakamura; Koji Sakui; Hideko Oodaira; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka; Hisashi Hara (IEEE J. Solid State Circuits, 1994)

A 2/3-in 2 million pixel STACK-CCD HDTV imager. - Hirofumi Yamashita; Michio Sasaki; Shinji Ohsawa; Ryohei Miyagawa; Eiji Ohba; Keiji Mabuchi; Nobuo Nakamura; Nagataka Tanaka; Nahoko Endoh; Ikuko Inoue; Yoshiyuki Matsunaga; Yoshitaka Egawa; et al. (IEEE J. Solid State Circuits, 1995)

New three-dimensional memory array architecture for future ultrahigh-density DRAM. - Tetsuo Endoh; Katsuhisa Shinmei; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 1999)

An on-chip 96.5% current efficiency CMOS linear regulator. - Kazuhisa Sunaga; Tetsuo Endoh; Hiroshi Sakuraba; Fujio Masuoka (ASP-DAC, 2001)

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. - Tetsuo Endoh; Kazuhisa Sunaga; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. - Akira Tanabe; Masato Umetani; Ikuo Fujiwara; Takayuki Ogura; Kotaro Kataoka; Masao Okihara; Hiroshi Sakuraba; Tetsuo Endoh; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering. - Yasue Yamamoto; Takeshi Hidaka; Hiroki Nakamura; Hiroshi Sakuraba; Fujio Masuoka (IEICE Trans. Electron., 2006)

A New Architecture for High-Density High-Performance SGT nor Flash Memory. - Takuya Kadowaki; Yoshizumi Yamakawa; Hiroki Nakamura; Yasuo Kimura; Michio Niwano; Fujio Masuoka (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. - Yisuo Li; Ken'ichi Kanazawa; Tetsuo Izawa; Koji Sakui; Georg Strof; Oskar Baumgartner; Gerhard Rzepa; Markus Karner; Zlatan Stanojevic; Nozomu Harada; Fujio Masuoka (IMW, 2021)