An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. - Masaki Momodomi; Yasuo Itoh; Riichiro Shirota; Yoshihisa Iwata; Ryozo Nakayama; Ryouhei Kirisawa; Tomoharu Tanaka; Seiichi Aritome; Tetsuo Endoh; Kazunori Ohuchi; Fujjo Masuoka (IEEE J. Solid State Circuits, 1989)