An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. - Katsuhiro Suma; Takahiro Tsuruda; Hideto Hidaka; Takahisa Eimori; Toshiyuki Oashi; Yasuo Yamaguchi; Toshiaki Iwamatsu; Masakazu Hirose; Fukashi Morishita; Kazutarni Arimoto; Kazuyasu Fujishima; Yasuo Inoue; et al. (IEEE J. Solid State Circuits, 1994)

SOI-DRAM circuit technologies for low power high speed multigiga scale memories. - Shigehiro Kuge; Fukashi Morishita; Takahiro Tsuruda; Shigeki Tomishima; Masaki Tsukude; Tadato Yamagata; Kazutami Arimoto (IEEE J. Solid State Circuits, 1996)

High-performance embedded SOI DRAM architecture for the low-power supply. - Tadaaki Yamauchi; Fukashi Morishita; Shigenobu Maeda; Kazutami Arimoto; Kazuyasu Fujishima; Hideyuki Ozaki; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2000)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs. - Takeshi Fujino; Akira Yamazaki; Yasuhiko Taito; Mitsuya Kinoshita; Fukashi Morishita; Teruhiko Amano; Masaru Haraguchi; Makoto Hatakenaka; Atsushi Amo; Atsushi Hachisuka; Kazutami Arimoto; Hideyuki Ozaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A capacitorless twin-transistor random access memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (CICC, 2005)

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. - Hideyuki Noda; Katsumi Dosaka; Fukashi Morishita; Kazutami Arimoto (CICC, 2005)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. - Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. - Masahisa Iida; Naoki Kuroda; Hidefumi Otsuka; Masanobu Hirose; Yuji Yamasaki; Kiyoto Ohta; Kazuhiko Shimakawa; Takashi Nakabayashi; Hiroyuki Yamauchi; Tomohiko Sano; Takayuki Gyohten; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2005)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Tetsushi Tanizaki; Takashi Ipposhi; Katsumi Dosaka (CICC, 2006)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. - Hideyuki Noda; Katsumi Dosaka; Hans Jürgen Mattausch; Tetsushi Koide; Fukashi Morishita; Kazutami Arimoto (IEICE Trans. Electron., 2006)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Isamu Hayashi; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Katsumi Dosaka; Hiroki Shimano; Takashi Ipposhi (IEEE J. Solid State Circuits, 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2009)

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. - Kazuhiro Ueda; Fukashi Morishita; Shunsuke Okura; Leona Okamura; Tsutomu Yoshihara; Kazutami Arimoto (IEEE J. Solid State Circuits, 2013)

A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit. - Shunsuke Okura; Osamu Nishikido; Yusuke Sadanaga; Yasuhiro Kosaka; Norihiko Araki; Kazuhiro Ueda; Masanori Tachibana; Fukashi Morishita (VLSIC, 2014)

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. - Shunsuke Okura; Osamu Nishikido; Yusuke Sadanaga; Yasuhiro Kosaka; Norihiko Araki; Kazuhiro Ueda; Fukashi Morishita (IEEE J. Solid State Circuits, 2015)

An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor. - Fukashi Morishita; Masanori Otsuka; Wataru Saito (ATS, 2020)

A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator. - Wataru Saito; Yoichi Iizuka; Norihito Kato; Ryota Otake; Fukashi Morishita (A-SSCC, 2021)

A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems. - Fukashi Morishita; Norihito Kato; Satoshi Okubo; Takao Toi; Mitsuru Hiraki; Sugako Otani; Hideaki Abe; Yuji Shinohara; Hiroyuki Kondo (VLSI Circuits, 2021)

High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor. - Fukashi Morishita; Wataru Saito; Norihito Kato; Yoichi Iizuka; Masao Ito (IEICE Trans. Electron., 2022)

A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera. - Fukashi Morishita; Wataru Saito; Yoichi Iizuka; Norihito Kato; Ryota Otake; Masao Ito (IEEE J. Solid State Circuits, 2022)

Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor. - Norihito Kato; Fukashi Morishita; Satoshi Okubo; Masao Ito (Sensors, 2022)

A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System. - Yoichi Iizuka; Akihide Maezono; Wataru Saito; Atsushi Yamane; Kazuhiko Takami; Fukashi Morishita (A-SSCC, 2023)

A Compact Optical Image Stabilization Chip with Actuator Trackability Improvement Controller and Double Offset Cancel Hall Amplifier to Improve Camera Shake Correction. - Wataru Saito; Yoichi Iizuka; Tetsuya Takahashi; Toshiya Suzuki; Hiroto Suzuki; Masatomo Shoji; Fukashi Morishita (A-SSCC, 2024)

A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler. - Yoichi Iizuka; Akihide Maezono; Wataru Saito; Kazuhiko Takami; Fukashi Morishita (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)