A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle. - Shuaiqi Wang; Fule Li; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Pipelined A/D Conversion Technique with Low INL and DNL. - Jingbo Duan; Fule Li; Liyuan Liu; Dongmei Li; Yongming Li 004; Zhihua Wang 001 (ISCAS, 2007)

An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters. - Fule Li; Zhihua Wang 001; Dongmei Li (ISCAS, 2007)

A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique. - Shuaiqi Wang; Fule Li; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique. - Qiuling Zhu; Chun Zhang; Zhongqi Liu; Jingchao Wang; Fule Li; Zhihua Wang 001 (ISCAS, 2009)

An energy-efficient SoC for closed-loop medical monitoring and intervention. - Xiaoyu Zhang; Hanjun Jiang; Fule Li; Songyuan Cheng; Chun Zhang; Zhihua Wang 001 (CICC, 2010)

A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end. - Xuan Wang; Changyi Yang; Xiaoxiao Zhao; Chao Wu; Fule Li; Zhihua Wang 001; Bin Wu (ISCAS, 2012)

A current-to-voltage integrator using area-efficient correlated double sampling technique. - Xuqiang Zheng; Fule Li; Xuan Wang; Chun Zhang (ISCAS, 2012)

A 14-bit pipelined ADC with digital background nonlinearity calibration. - Weitao Li; Cao Sun; Fule Li; Zhihua Wang 001 (ISCAS, 2013)

A merged first and second stage for low power pipelined ADC. - Changyi Yang; Weitao Li; Fule Li; Zhihua Wang 001 (ISCAS, 2013)

A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue. - Lingwei Zhang 001; Hanjun Jiang; Fule Li; Jingjing Dong; Zhihua Wang 001 (ISCAS, 2013)

An efficient calibration technique for pipeline ADC. - Chenchen Zhao; Lili Xu; Fule Li; Zhihua Wang 001 (MWSCAS, 2013)

Lifetime tracing of cardiopulmonary sounds with ultra-low-power sound sensor stick connected to wireless mobile network. - Zhihua Wang 001; Hanjun Jiang; Kai Yang; Lingwei Zhang 001; Jianjun Wei; Fule Li; Baoyong Chi; Chun Zhang; Shouhao Wu; Qingliang Lin; Wen Jia (NEWCAS, 2013)

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO. - Lingwei Zhang 001; Hanjun Jiang; Jianjun Wei; Jingjing Dong; Fule Li; Weitao Li; Jia Gao; Jianwei Cui; Baoyong Chi; Chun Zhang; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2013)

A low-power DC offset calibration method independent of IF gain for zero-IF receiver. - Jingjing Dong; Hanjun Jiang; Lingwei Zhang 001; Jianjun Wei; Fule Li; Chun Zhang; Zhihua Wang 001 (Sci. China Inf. Sci., 2014)

A calibration technique for SAR ADC based on code density test. - Xian Gu; XiuJu He; Fule Li (ASICON, 2015)

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. - Fangxu Lv; Xuqiang Zheng; Ziqiang Wang; Jianye Wang; Fule Li (ASICON, 2015)

A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC. - Meng Ni; Fule Li; Weitao Li; Chun Zhang; Zhihua Wang 001 (ASICON, 2015)

Dedicated ICs for wearable body sound monitoring. - Zhaoyang Weng; Shaoquan Gao; Jingjing Dong; Kai Yang; Hanjun Jiang; Fule Li; Zhihua Wang 001; Yanqing Ning; Xinkai Chen (A-SSCC, 2015)

A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. - Ke Huang 003; Deng Luo; Ziqiang Wang; Xuqiang Zheng; Fule Li; Chun Zhang; Zhihua Wang 001 (CICC, 2015)

Charge-compensation-based reference technique for switched-capacitor ADCs. - Ya Wang; Fule Li; Chunying Xue; Zhihua Wang 001 (ISCAS, 2015)

A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. - Weidong Cao 001; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Fule Li; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2015)

A 14-bit 200MS/s low-power pipelined flash-SAR ADC. - Jifang Wu; Fule Li; Weitao Li; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2015)

A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. - Weidong Cao 001; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Ke Huang 003; Shuai Yuan 005; Fule Li; Zhihua Wang 001 (NEWCAS, 2015)

A digital blind background calibration algorithm for pipelined ADC. - Shengjing Li; Weitao Li; Fule Li; Zhihua Wang 001; Chun Zhang (NEWCAS, 2015)

A power-efficient 14-bit 250MS/s pipelined ADC. - Weitao Li; Fule Li; Ya Wang; Shengjing Li; Chun Zhang; Zhihua Wang 001 (NEWCAS, 2015)

A power-efficient reference buffer with wide swing for switched-capacitor ADC. - Weitao Li; Fule Li; Changyi Yang; Minzeng Li; Zhihua Wang 001 (Microelectron. J., 2015)

A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication. - Qi Peng; Chun Zhang; Xijin Zhao; Xuguang Sun; Fule Li; Hong Chen 002; Zhihua Wang 001 (IEEE Trans. Ind. Electron., 2015)

An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. - Xuqiang Zheng; Chun Zhang; Shuai Yuan 005; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001 (A-SSCC, 2016)

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001 (ESSCIRC, 2016)

A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. - Xiao Wang 021; Fule Li; Zhihua Wang 001 (ISCAS, 2016)

Aperture error reduction technique for subrange SAR ADC. - Ying Ju; Fule Li; XiuJu He; Chun Zhang; Zhihua Wang 001 (NEWCAS, 2016)

An 11-bit 200MS/s subrange SAR ADC with charge-compensation-based reference buffer. - Shushu Wei; Ying Ju; Fule Li; Zhihua Wang 001 (NEWCAS, 2016)

High speed serial interface transceiver controller based on JESD204B. - Zhaoming Wu; Chun Zhang; Fule Li; Zhihua Wang 001 (NEWCAS, 2016)

A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. - Naiwen Zhou; Linghan Wu; Ziqiang Wang; Xuqiang Zheng; Weidong Cao 001; Chun Zhang; Fule Li; Zhihua Wang 001 (NEWCAS, 2016)

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. - Xuqiang Zheng; Zhijun Wang; Fule Li; Feng Zhao 004; Shigang Yue; Chun Zhang; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier. - Honghao Chu; Fule Li (ASICON, 2017)

A low-offset dynamic comparator with input offset-cancellation. - Ruihan Pei; Jia Liu; Xian Tang; Fule Li; Zhihua Wang 001 (ASICON, 2017)

A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. - Weitao Li; Fule Li; Jia Liu; Hongyu Li; Zhihua Wang 001 (A-SSCC, 2017)

A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. - Xuqiang Zheng; Fangxu Lv; Feng Zhao 004; Shigang Yue; Chun Zhang; Ziqiang Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (CICC, 2017)

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (CICC, 2017)

A Wireless Body Sound Sensor with a Dedicated Compact Chipset. - Jingjing Dong; Hanjun Jiang; Kai Yang; Zhaoyang Weng; Fule Li; Jianjun Wei; Yanqing Ning; Xinkai Chen; Zhihua Wang 001 (Circuits Syst. Signal Process., 2017)

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shuai Yuan 005; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001; Hanjun Jiang (IEEE J. Solid State Circuits, 2017)

A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. - Chengwei Wang; Xiao Wang 021; Yang Ding; Fule Li; Zhihua Wang 001 (ISCAS, 2018)

A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. - Xiao Wang 021; Chengwei Wang; Fule Li; Zhihua Wang 001 (ISCAS, 2018)

400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna. - Zhaoyang Weng; Hanjun Jiang; Jingjing Dong; Yang Li; Jingyi Zheng; Yiyu Shen; Fule Li; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

DCO gain calibration technique in fractional-N Δ-Σ PLL based two-point phase modulators. - Shaoquan Gao; Hanjun Jiang; Fule Li; Zhihua Wang 001 (MWSCAS, 2019)

A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration. - Xiao Wang 021; Fule Li; Wen Jia; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. - Meng Ni; Xiao Wang 021; Zhe Zhou; Yang Ding; Fule Li; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2020)

A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. - Meng Ni; Xiao Wang 021; Zhe Zhou; Yang Ding; Fule Li; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2020)

A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers. - Shaoquan Gao; Hanjun Jiang; Fule Li; Zhihua Wang 001 (Sci. China Inf. Sci., 2020)

A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs. - Xiao Wang 021; Fule Li; Zhihua Wang 001 (IEEE Trans. Circuits Syst., 2020)

A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. - Peilin Yang; Xiao Wang 021; Chengwei Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 12-bit 800MS/s pipelined A/D converter. - Haoran Wang; Fule Li (ASICON, 2021)

A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC. - Peilin Yang; Fule Li; Zhihua Wang 001 (ISCAS, 2021)

A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. - Meng Ni; Xiao Wang 021; Fule Li; Zhihua Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A statistics-based background capacitor mismatch calibration algorithm for SAR ADC. - Zhiqiang Luo; Peng Wang; Fule Li; Chun Zhang; Zhihua Wang 001 (ICTA, 2022)

A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs. - Haoran Wang; Junjie Jing; Fule Li (ISCAS, 2022)

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. - Meng Ni; Xiao Wang 021; Fule Li; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation. - Yihang Cheng 003; Yaning Wang; Fule Li; Chun Zhang; Zhihua Wang 001 (ISCAS, 2023)

Current-Steering DAC Calibration Using Q-Learning. - Yaoyu Li; Yanshu Guo; Wen Jia; Fule Li; Zhihua Wang 001; Hanjun Jiang (ISCAS, 2023)

All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture. - Zhiqiang Luo; Peng Wang 004; Jingpeng Zhou; Fule Li (ISCAS, 2023)

A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing. - Junjie Jing; Yang Ding; Lingxiao Shen; Peng Wang; Fule Li (NEWCAS, 2023)

A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input. - Yaning Wang; Yihang Cheng 003; Yongli Chen; Fule Li; Chun Zhang; Zhihua Wang 001 (NEWCAS, 2023)

A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer. - Chen Chen 040; Fangzhen Jiang; Peng Wang 117; Yongli Chen; Yan Xiao; Fule Li; Xiang Xie (ISCAS, 2024)

A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs. - Yaning Wang; Zhenguo Li; Peng Wang; Yihang Cheng 003; Fule Li; Yi Hu; Jiali Hou; Meng Su; Mengjiao Li (ISCAS, 2024)

A 3-MHz-3-GHz 8-Phase Reset-Free Anti-Harmonic Delay-Locked Loop Using Phase Difference Composition in 65-nm CMOS. - Jianming Pan; Meng Su; Fule Li; Yidong Yuan; Yi Hu; Zhenguo Li; Rui Zhang; Jiali Hou; Yabin Wang (MWSCAS, 2024)

A High Linearity ADC Front-End Circuit for Single-Ended Inputs. - Rui Zhang; Yabin Wang; Fule Li; Yidong Yuan; Yi Hu; Hongwei Shen; Zhenguo Li; Jiaming Pan; Jiali Hou (MWSCAS, 2024)

Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach. - Hailong Xing; Yonggui Kao; Guangbin Wang; Fule Li (Eur. J. Control, 2024)

Corrigendum to 'Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach' [European Journal of Control 77 (2024) 100984]. - Hailong Xing; Yonggui Kao 001; Guangbin Wang; Fule Li (Eur. J. Control, 2024)

A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning. - Peilin Yang; Fule Li; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A SHA-Less Front-end Stage Structure Suitable for Time-Interleaved Pipeline ADC. - Meng Ni; Peng Wang; Fule Li; Hanjun Jiang; Zhihua Wang (ISCAS, 2025)

A 550MHz-B and width 40dB-Gain Range Analog Baseband with Dynamic PVT Compensation Achieving 26.1 dBm OIP3 in 28-nm CMOS. - Guo Wei; Xuanyan Liu; Tian Tian; Yanshu Guo; Wenqiang Huang; Fule Li; Zhihua Wang 001; Hanjun Jiang (ISCAS, 2025)

A High-Speed High-Precision Comparator with Offset Calibration for SHA_less Pipeline ADCs. - Shuoxiong Yang; Dejian Li; Peng Wang; Fule Li; Zhihua Wang 001 (ISCAS, 2025)

A Dynamic Biasing Circuit for Low-Power Push-Pull Input Buffer. - Rui Zhang; Yidong Yuan; Peng Wang; Lingxiao Shen; Fule Li; Zhihua Wang; Yi Hu; Zhenguo Li (ISCAS, 2025)

A Single-Channel 8-bit 1.6-GS/s Alternate-Comparator SAR ADC With Dither-Based Background Offset Calibration in 28-nm CMOS. - Peng Wang; Fule Li; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)